Introduction to Systemverilog (Hardcover)

Mehta, Ashok B.

  • 出版商: Springer
  • 出版日期: 2021-07-07
  • 售價: $5,690
  • 貴賓價: 9.5$5,406
  • 語言: 英文
  • 頁數: 852
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 3030713180
  • ISBN-13: 9783030713188
  • 相關分類: Verilog
  • 其他版本: Introduction to Systemverilog (美國原版)
  • 無法訂購

商品描述

作者簡介

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on "SystemVerilog Assertions and Functional Coverage" and second on "ASIC Functional Design Verification - A guide to technologies and methodologies". His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

作者簡介(中文翻譯)

Ashok Mehta是一位在半導體行業擁有超過30年經驗的ASIC/CPU設計和驗證工程師。他曾在DEC、Data General、Intel、Applied Micro和TSMC等公司工作。他是Verilog技術小組的早期成員之一。他在ASIC和3DIC設計和驗證領域擁有19項美國專利。他還是兩本受歡迎的書籍的作者,一本是關於「SystemVerilog斷言和功能覆蓋」,另一本是關於「ASIC功能設計驗證-技術和方法論指南」。他目前的興趣包括3DIC半導體設計驗證、系統級建模(虛擬平台)和一般驗證方法論。

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