Formal Verification of Floating-Point Hardware Design: A Mathematical Approach

This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design, Second Edition advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations.

As a basis for the formal verification of such implementations, high-level specifications of the basic arithmetic instructions of several major industry-standard floating-point architectures are presented, including all details pertaining to the handling of exceptional conditions. The methodology is illustrated in the comprehensive verification of a variety of state-of-the-art commercial floating-point designs developed by Arm Holdings.

This revised edition reflects the evolving microarchitectures and increasing sophistication of Arm processors, and the variation in the design goals of execution speed, hardware area requirements, and power consumption. Many new results have been added to Parts I--III (Register-Transfer Logic, Floating-Point Arithmetic, and Implementation of Elementary Operations), extending the theory and describing new techniques. These were derived as required in the verification of the new RTL designs described in Part V.

這是第一本專注於通過數學方法確保浮點硬體設計正確性的書籍。《浮點硬體設計的形式驗證，第二版》提出了一種基於統一的寄存器傳輸邏輯和浮點算術的驗證方法論，該方法論已經在商業浮點單元的形式驗證中得到了發展和應用，作者在此期間曾在幾家主要微處理器設計公司工作。該理論被擴展到分析幾種在商業實現中常用的算法和優化技術。

為了對這些實現進行形式驗證，本書提供了幾個主要行業標準浮點架構的基本算術指令的高級規格，包括處理異常情況的所有細節。該方法論在對Arm Holdings開發的各種最新商業浮點設計進行全面驗證時進行了演示。

此修訂版反映了Arm處理器的演進微架構和日益複雜的設計目標變化，包括執行速度、硬體面積需求和功耗。在第I至III部分（寄存器傳輸邏輯、浮點算術和基本操作的實現）中增加了許多新結果，擴展了理論並描述了新技術。這些結果是根據第V部分中描述的新RTL設計的驗證需求而得出的。

David M. Russinoff is Senior Principal Engineer at Arm Holdings. He holds a bachelor's degree from the Massachusetts Institute of Technology and a doctorate from New York University, both in mathematics, and a master's in computer sciences from the University of Texas at Austin. He has spent twenty-five years developing mathematical methods of hardware verification, with an emphasis on interactive theorem proving, and applying them in the analysis of commercial designs, especially arithmetic circuits.

David M. Russinoff 是 Arm Holdings 的高級主任工程師。他擁有麻省理工學院的學士學位和紐約大學的博士學位，兩者都是數學專業，並且還擁有德克薩斯大學奧斯汀分校的計算機科學碩士學位。他已經花了二十五年的時間開發數學方法來進行硬體驗證，尤其是互動式定理證明，並且應用這些方法在商業設計中進行分析，特別是算術電路。