This book focuses on neuromorphic computing principles and organization and how to build fault-tolerant scalable hardware for large and medium scale spiking neural networks with learning capabilities. In addition, the book describes in a comprehensive way the organization and how to design a spike-based neuromorphic system to perform network of spiking neurons communication, computing, and adaptive learning for emerging AI applications. The book begins with an overview of neuromorphic computing systems and explores the fundamental concepts of artificial neural networks. Next, we discuss artificial neurons and how they have evolved in their representation of biological neuronal dynamics. Afterward, we discuss implementing these neural networks in neuron models, storage technologies, inter-neuron communication networks, learning, and various design approaches. Then, comes the fundamental design principle to build an efficient neuromorphic system in hardware. The challenges that need to be solved toward building a spiking neural network architecture with many synapses are discussed. Learning in neuromorphic computing systems and the major emerging memory technologies that promise neuromorphic computing are then given.
A particular chapter of this book is dedicated to the circuits and architectures used for communication in neuromorphic systems. In particular, the Network-on-Chip fabric is introduced for receiving and transmitting spikes following the Address Event Representation (AER) protocol and the memory accessing method. In addition, the interconnect design principle is covered to help understand the overall concept of on-chip and off-chip communication. Advanced on-chip interconnect technologies, including si-photonic three-dimensional interconnects and fault-tolerant routing algorithms, are also given. The book also covers the main threats of reliability and discusses several recovery methods for multicore neuromorphic systems. This is important for reliable processing in several embedded neuromorphic applications. A reconfigurable design approach that supports multiple target applications via dynamic reconfigurability, network topology independence, and network expandability is also described in the subsequent chapters. The book ends with a case study about a real hardware-software design of a reliable three-dimensional digital neuromorphic processor geared explicitly toward the 3D-ICs biological brain's three-dimensional structure. The platform enables high integration density and slight spike delay of spiking networks and features a scalable design. We present methods for fault detection and recovery in a neuromorphic system as well.
Neuromorphic Computing Principles and Organization is an excellent resource for researchers, scientists, graduate students, and hardware-software engineers dealing with the ever-increasing demands on fault-tolerance, scalability, and low power consumption. It is also an excellent resource for teaching advanced undergraduate and graduate students about the fundamentals concepts, organization, and actual hardware-software design of reliable neuromorphic systems with learning and fault-tolerance capabilities.
本書專注於神經形態計算的原則和組織，以及如何建立可容錯且可擴展的硬體，用於具有學習能力的大型和中型脈衝神經網絡。此外，本書全面描述了如何設計基於脈衝的神經形態系統，以執行脈衝神經元網絡的通信、計算和自適應學習，以應用於新興的人工智能應用。本書首先概述了神經形態計算系統，並探討了人工神經網絡的基本概念。接下來，我們討論了人工神經元及其在生物神經元動力學表示方面的演變。然後，我們討論了在神經元模型、存儲技術、神經元間通信網絡、學習和各種設計方法中實現這些神經網絡的方法。接著，介紹了在硬體中建立高效神經形態系統的基本設計原則。討論了建立具有多個突觸的脈衝神經網絡架構所需解決的挑戰。然後，介紹了神經形態計算系統中的學習和主要新興記憶技術。
本書的一個特定章節專門介紹了神經形態系統中用於通信的電路和架構。特別介紹了用於接收和傳輸脈衝的片上網絡（Network-on-Chip fabric），遵循地址事件表示（AER）協議和記憶體訪問方法。此外，還介紹了片上和片外通信的互連設計原則。還介紹了先進的片上互連技術，包括矽光三維互連和容錯路由算法。本書還涵蓋了可靠性的主要威脅，並討論了多核神經形態系統的幾種恢復方法。這對於多個嵌入式神經形態應用中的可靠處理非常重要。本書還描述了一種可重配置的設計方法，通過動態可重配置性、網絡拓撲獨立性和網絡可擴展性，支持多個目標應用。本書以一個實際的硬體-軟體設計案例結束，該案例專門針對三維集成電路（3D-ICs）生物大腦的三維結構。該平台實現了高集成密度和微小的脈衝延遲，並具有可擴展的設計。我們還介紹了神經形態系統中的故障檢測和恢復方法。
《神經形態計算原則與組織》是研究人員、科學家、研究生和硬體-軟體工程師的優秀資源，他們面臨著對容錯性、可擴展性和低功耗的不斷增長需求。對於教授高級本科和研究生學生有關可靠神經形態系統的基本概念、組織和實際硬體-軟體設計的課程，本書也是一個優秀的資源。
Abderazek Ben Abdallah is a Full Professor of Computer Science and Engineering, University of Aizu, Aizu-Wakamatus, Japan, since April 2014. He has more than 20- years of experience in research and education of computer systems design and adaptive brain-inspired computing systems. His current research interest lies in studying neural processing systems with a particular focus on spike-based neural network dynamics and spike-based learning. He has authored three books, holds 4 registered and 5 pending Japanese patents, received numerous awards, and published more than 160 journal articles and conference papers.
Khanh N. Dang received his Ph.D. degree from The University of Aizu, Japan in 2017. Since 2017, he has been an assistant professor at VNU Key Laboratory for Smart Integrated Systems, VNU University of Engineering and Technology, Vietnam National University Hanoi (VNU), Hanoi Vietnam. He was a visiting researcher at the University of Aizu in 2019 and 2020-2021. His research interests include neuromorphic computing, 3D Integrated Circuits technology, AI for CAD, and fault-tolerance.
Abderazek Ben Abdallah是日本會津大學（University of Aizu）的計算機科學與工程學的全職教授，自2014年4月起擔任該職位。他在計算機系統設計和適應性腦啟發計算系統的研究和教育方面擁有超過20年的經驗。他目前的研究興趣在於研究神經處理系統，特別關注基於脈衝的神經網絡動態和基於脈衝的學習。他撰寫了三本書，擁有4項已註冊和5項待註冊的日本專利，並獲得了眾多獎項，發表了160多篇期刊文章和會議論文。
Khanh N. Dang於2017年從日本會津大學獲得博士學位。自2017年以來，他一直擔任越南國家大學河內分校（VNU University of Engineering and Technology）智能集成系統VNU重點實驗室（VNU Key Laboratory for Smart Integrated Systems）的助理教授。他在2019年和2020-2021年期間曾是會津大學的訪問研究員。他的研究興趣包括神經形態計算、三維集成電路技術、CAD的人工智能和容錯性。
