Design and Modeling of PLL Based CDR for Inter Chip Communications: Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery ... Gb/s Intra/Inter Chip Communications in SoC (Paperback)

Maher Assaad

  • 出版商: VDM Verlag
  • 出版日期: 2009-10-09
  • 售價: $2,890
  • 貴賓價: 9.5$2,746
  • 語言: 英文
  • 頁數: 148
  • 裝訂: Paperback
  • ISBN: 3639185544
  • ISBN-13: 9783639185546
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)



This work describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the proposed concept. The frequency-locked loop (FLL) operates independently from the phase-locked loop (PLL), and has a highly-desired feature that once the proper frequency has been acquired, the FLL is automatically disabled and the PLL will take over to adjust the clock edges approximately in the middle of the incoming data bits for proper sampling. Another important feature of the proposed quarter-rate concept is the inherent 1-to-4 demultiplexing of the input serial data stream. In order to verify the accuracy of the proposed quarter-rate concept, a clockless asynchronous serial link incorporating the proposed concept and communicating two chips at 10 Gb/s has been modeled at gate level using the Verilog-A language and time-domain simulated.


本著作描述了一個完全單片式的10 Gb/s相位和頻率鎖定迴路(PFLL-CDR)集成電路的設計和實現,以及基於所提出的概念的異步串行連接芯片之間通信系統的Verilog-A建模。頻率鎖定迴路(FLL)獨立於相位鎖定迴路(PLL)運作,具有一個非常理想的特點,即一旦獲得正確的頻率,FLL將自動停用,PLL將接管調整時鐘邊緣,以便在接收數據位的中間進行正確的取樣。所提出的四分之一速率概念的另一個重要特點是輸入串行數據流的固有1對4解多路。為了驗證所提出的四分之一速率概念的準確性,使用Verilog-A語言和時域模擬,在閘級上建模了一個以時鐘為基礎的異步串行連接,以10 Gb/s的速率通信兩個芯片。