iLAB Digital: Circuit Design,Simulation, and Testing (Paperback)
暫譯: iLAB 數位：電路設計、模擬與測試 (平裝本)

Kai-Tai Chen , Yun-Chao Chen

iLAB Digital: Circuit Design,Simulation, and Testing (Paperback)
  • 出版商: 新月圖書
  • 出版日期: 2018-01-01
  • 售價: $825
  • 貴賓價: 9.8 折 $809
  • 語言: 英文
  • 頁數: 256
  • ISBN: 9869614108
  • ISBN-13: 9789869614108
  • 相關分類: 邏輯設計 Logic-design

    • 下單後立即進貨 (約5~7天)

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商品描述

Foreword
iLAB-Digital is the second volume and is similar to the first volume iLAB Analog for the purpose of using the Analog Discovery module. It is specifically written for electronic circuit design at the Technology-College Level. A total of 13 chapters at 3 hours per week is designed to fit a semester-duration course of study. The first through the sixth chapter cover the basic logic circuit design including Logic Gates, Adders, JKFFs, MUX/DEMUXs, Shift Registers and Counters. Chapter 7 through 11 cover Digital-to-Analog Conversion, Analog-to-Digital Conversion, Clocks, PLLs, Steppers, Drivers, Servos and Controls. Chapter 12 through 13 cover basic logic circuits for Altera and Xilinx platform FPGAs and their corresponding synthesis.

Each chapter contains:

  1. Description of circuit configuration;
  2. VHDL description of the circuit composition simulation;
  3. Layout and implementation of circuit structure;
  4. Using Analog Discovery to test and debug the circuit;
  5. Chapter Exercises to reinforce newly learned content.


The time distribution for coursework success is namely:

  1. For instructor lecture using chapter items 1 through 3 including answering student questions, 1 hour;
  2. Post-lecture, students studying course material by following chapter item 2 for up to 1 hour;
  3. Post lecture, students must repeat the examples given in chapter items 3 to 4 for up to 1 hour;
  4. In addition to completing the end of chapter exercises, students must overcome the unsuccessful simulation and debugging of the circuit using the Analog Discovery module, which is estimated at between 4 to 8 hours.


Required equipment and tools:

  1. Software: VHDL simulation test software may be downloaded from the Altera/Quartus website. If using Xilinx FPGAs for synthesis, the software may be downloaded from the Xilinx/ISE website. Waveform test software is available from Digilent’s website. All of the indicated software is available for download free of charge.
  2. Hardware: From the first through the eleventh chapter, the electronic components specified are common and available at low cost from a wide variety of electronic component shops throughout the island. Chapter 12 of the FPGA implementation requires the Altera/Terasic DE2-115. Chapter 13 of the FPGA implementation requires the Xilinx/Digilent BASYS3. Because iLAB-Digital uses Digilent/Analog Discovery’s Digital Pattern Generator and Logic Analyzer for evaluation, it works nearly independently of the FPGA implementation platform.

商品描述(中文翻譯)

前言
iLAB-Digital 是第二卷，與第一卷 iLAB Analog 類似，旨在使用 Analog Discovery 模組。它專門為技術學院層級的電子電路設計而撰寫。共計 13 章，每週 3 小時，設計為一學期的課程。第一至第六章涵蓋基本邏輯電路設計，包括邏輯閘、加法器、JK 觸發器、MUX/DEMUX、移位暫存器和計數器。第七至第十一章涵蓋數位轉類比轉換、類比轉數位轉換、時鐘、相位鎖定迴路 (PLLs)、步進馬達、驅動器、伺服機和控制。第十二至第十三章涵蓋 Altera 和 Xilinx 平台 FPGA 的基本邏輯電路及其相應的綜合。

每章包含：

1. 電路配置的描述；
2. 電路組成模擬的 VHDL 描述；
3. 電路結構的佈局和實現；
4. 使用 Analog Discovery 測試和除錯電路；
5. 章末練習以鞏固新學習的內容。

課程成功的時間分配如下：

1. 教師講解第 1 至第 3 項內容，包括回答學生問題，1 小時；
2. 講課後，學生根據第 2 項內容學習課程材料，最多 1 小時；
3. 講課後，學生必須重複第 3 至第 4 項中的範例，最多 1 小時；
4. 除了完成章末練習外，學生必須克服使用 Analog Discovery 模組進行電路模擬和除錯的失敗，預計需要 4 至 8 小時。

所需設備和工具：

1. 軟體：VHDL 模擬測試軟體可從 Altera/Quartus 網站下載。如果使用 Xilinx FPGA 進行綜合，則可從 Xilinx/ISE 網站下載該軟體。波形測試軟體可從 Digilent 的網站獲得。所有指示的軟體均可免費下載。
2. 硬體：從第一章到第十一章，指定的電子元件是常見的，並且可以在全島各種電子元件商店以低成本獲得。第十二章的 FPGA 實現需要 Altera/Terasic DE2-115。第十三章的 FPGA 實現需要 Xilinx/Digilent BASYS3。由於 iLAB-Digital 使用 Digilent/Analog Discovery 的數位模式產生器和邏輯分析儀進行評估，因此它幾乎獨立於 FPGA 實現平台。

目錄大綱

目　錄
Chapter 1 Using NAND Logic Gates to Synthesize Other Logic Gates 
Chapter 2 Evaluating the Adder
Chapter 3 JKFF Composition and Evaluation
Chapter 4  Data Selectors and Multiplexers/Demultiplexers
Chapter 5  Shift Registers
Chapter 6 Counters
Chapter 7 Digital to Analog Conversion
Chapter 8 Analog to Digital Conversion
Chapter 9 Clock Generation and PLL
Chapter 10 Stepping Motor and Driver
Chapter 11 Servo System and Control
Chapter 12 The Altera/Quartus DE2-115 FPGA Evaluation Kit
Chapter 13  Xilinx/Vivado Basys3 FPGA Synthesis

Appendix A  VHDL Circuit Format and Structure
Appendix B  VHDL Testbench Structure and Stimulus File
Appendix C  Creating and Using Digital Patterns
Appendix D  Using the Logic Analyzer
Appendix E  ModelSim Simulation and Testing
Appendix F  Using the LM565 PLL
Appendix G  Xilinx CPLD Circuit Synthesis
Glossary

目錄大綱(中文翻譯)

目　錄

Chapter 1 Using NAND Logic Gates to Synthesize Other Logic Gates 

Chapter 2 Evaluating the Adder

Chapter 3 JKFF Composition and Evaluation

Chapter 4  Data Selectors and Multiplexers/Demultiplexers

Chapter 5  Shift Registers

Chapter 6 Counters

Chapter 7 Digital to Analog Conversion

Chapter 8 Analog to Digital Conversion

Chapter 9 Clock Generation and PLL

Chapter 10 Stepping Motor and Driver

Chapter 11 Servo System and Control

Chapter 12 The Altera/Quartus DE2-115 FPGA Evaluation Kit

Chapter 13  Xilinx/Vivado Basys3 FPGA Synthesis



Appendix A  VHDL Circuit Format and Structure

Appendix B  VHDL Testbench Structure and Stimulus File

Appendix C  Creating and Using Digital Patterns

Appendix D  Using the Logic Analyzer

Appendix E  ModelSim Simulation and Testing

Appendix F  Using the LM565 PLL

Appendix G  Xilinx CPLD Circuit Synthesis

Glossary

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