Design-for-Test for Digital IC's and Embeddes Core Systems
暫譯: 數位集成電路與嵌入式核心系統的測試設計

Alfred Crouch

Design-for-Test for Digital IC's and Embeddes Core Systems
  • 出版商: Prentice Hall
  • 出版日期: 1999-07-02
  • 售價: $1,760
  • 貴賓價: 9.8 折 $1,725
  • 語言: 英文
  • 頁數: 347
  • 裝訂: Paperback
  • ISBN: 0130848271
  • ISBN-13: 9780130848277
  • 相關分類: 電子電路電機類

    • 已絕版

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商品描述

Description:

8482G-5

The first practical DFT guide from an industry insider.

Skip the high-brow theories and mathematical formulas—get down to the business of digital design and testing as it's done in the real world. Learn practical testing strategies that address today's business needs for quality, reliability, and cost control, working within the tight deadlines of typical high-pressure production environments. Design-for-Test for Digital IC's and Embedded Core Systems helps you optimize the engineering trade-offs between such resources as silicon area, operating frequency, and power consumption, while balancing the corporate concerns of cost-of-test, time-to-market, and time-to-volume. You'll also boost your efficiency with the special focus on automatic test pattern generation (ATPG).

The book includes a roadmap that allows you to fine-tune your learning if you want to skip directly to a specific subject. Key topics include:

  • Core-based design, focusing on embedded cores and embedded memories
  • System-on-a-chip and ultra-large scale integrated design issues
  • AC scan, at-speed scan, and embedded DFT
  • Built-in self-test, including memory BIST, logic BIST, and scan BIST
  • Virtual test sockets and testing in isolation
  • Design for reuse, including reuse vectors and cores
  • Test issues being addressed by VSIA and the IEEE P1500 Standard

Design-for-Test for Digital IC's and Embedded Core Systems is filled with full-page graphics taken directly from the author's teaching materials. Every section is illustrated with flow-charts, engineering diagrams, and conceptual summaries to make learning and reference fast and easy. This book is a must for the engineers and managers involved in design and testing.

The enclosed CD-ROM contains full-color versions of all the book's illustrations in Acrobat PDF format. These images may be viewed interactively on screen or printed out to create overheads for teaching. Acrobat Reader software for Windows and UNIX computers is included.

 

Table of Contents:

Preface.


Acknowledgments.


Introduction.


1. Test and Design-for-Test Fundamentals.

Introduction to Test and DFT Fundamentals.

Purpose. Introduction to Test, the Test Process, and Design-for-Test. Concurrent Test Engineering.

The Reasons for Testing.

Why Test? Why Add Test Logic? Pro and Con Perceptions of DFT.

The Definition of Testing.

What Is Testing? Stimulus. Response.

Test Measurement Criteria.

What Is Measured? Fault Metric Mathematics.

Fault Modeling.

Physical Defects. Fault Modeling.

Types of Testing.

Functional Testing. Structural Testing. Combinational Exhaustive and Pseudo-Exhaustive Testing. Full Exhaustive Testing. Test Styles.

Manufacturing Test.

The Manufacturing Test Process. Manufacturing Test Load Board. Manufacturing Test Program.

Using Automatic Test Equipment.

Automatic Test Equipment. ATE Limitations. ATE Cost Considerations.

Test and Pin Timing.

Tester and Device Pin Timing. Tester Edge Sets. Tester Precision and Accuracy.

Manufacturing Test Program Components.

The Pieces and Parts of a Test Program. Test Program Optimization.

Recommended Reading.



2. Automatic Test Pattern Generation Fundamentals.

Introduction to Automatic Test Pattern Generation.

Purpose. Introduction to Automated Test Pattern Generation. The Vector Generation Process Flow.

The Reasons for ATPG.

Why ATPG? Pro and Con Perceptions of ATPG.

The Automatic Test Pattern Generation Process.

Introduction to ATPG.

Introducing the Combinational Stuck-At Fault.

Combinational Stuck-At Faults. Combinational Stuck-At Fault Detection.

Introducing the Delay Fault.

Delay Faults. Delay Fault Detection.

Introducing the Current-Based Fault.

Current-Based Testing. Current-Based Testing Detection.

Testability and Fault Analysis Methods.

Why Conduct ATPG Analysis or Testability Analysis? What Types of Testability Analysis Are Available? Fault Effective Circuits. Controllability-Observability Analysis. Circuit Learning.

Fault Masking.

Causes and Effects of Fault Masking. Fault Masking on Various Fault Models.

Stuck Fault Equivalence.

Fault Equivalence Optimization. Fault Equivalence Side Effects.

Stuck-At ATPG.

Fault Selection. Exercising the Fault. Detect Path Sensitization.

Transition Delay Fault ATPG.

Using ATPG with Transition Delay Faults. Transition Delay Is a Gross Delay Fault.

Path Delay Fault ATPG.

Path Delay ATPG. Robust Fault Detection. The Path Delay Design Description. Path Enumeration.

Current-Based Fault ATPG.

Current-Based ATPG Algorithms.

Combinational versus Sequential ATPG.

Multiple Cycle Sequential Test Pattern Generation. Multiple Time Frame Combinational ATPG. Two-Time-Frame ATPG Limitations. Cycle-Based ATPG Limitations.

Vector Simulation.

Fault Simulation. Simulation for Manufacturing Test.

ATPG Vectors.

Vector Formats. Vector Compaction and Compression.

ATPG-Based Design Rules.

The ATPG Tool "NO" Rules List. Exceptions to the Rules.

Selecting an ATPG Tool.

The Measurables. The ATPG Benchmark Process.

ATPG Fundamentals Summary.

Establishing an ATPG Methodology.

Recommended Reading.



3. Scan Architectures and Techniques.

Introduction to Scan-Based Testing.

Purpose. The Testing Problem. Scan Testing. Scan Testing Misconceptions.

Functional Testing. The Scan Effective Circuit. The Mux-D Style Scan Flip-Flops.

The Multiplexed-D Flip-Flop Scan Cell. Perceived Silicon Impact of the Mux-D Scan Flip-Flop. Other Types of Scan Flip-Flops. Mixing Scan Styles.

Preferred Mux-D Scan Flip-Flops.

Operation Priority of the Multiplexed-D Flip-Flop Scan Cell. The Mux-D Flip-Flop Family.

The Scan Shift Register or Scan Chain.

The Scan Architecture for Test. The Scan Shift Register (a.k.a The Scan Chain).

Scan Cell Operations.

Scan Cell Transfer Functions.

Scan Test Sequencing. Scan Test Timing. Safe Scan Shifting. Safe Scan Sampling: Contention-Free Vectors.

Contention-Free Vectors.

Partial Scan.

Scan Testing with Partial-Scan. Sequential ATPG.

Multiple Scan Chains.

Advantages of Multiple Scan Chains. Balanced Scan Chains.

The Borrowed Scan Interface.

Setting up a Borrowed Scan Interface. The Shared Scan Input Interface. The Shared Scan Output Interface.

Clocking, On-Chip Clock Sources, and Scan.

On-Chip Clock Sources and Scan Testing. On-Chip Clocks and Being Scan Tested.

Scan-Based Design Rules.

Scan-Based DFT and Design Rules. The Rules.

Stuck-At (DC) Scan Insertion.

DC Scan Insertion. Extras. DC Scan Insertion and Multiple Clock Domains.

Stuck-At Scan Diagnostics.

Implementing Stuck-At Scan Diagnostics. Diagnostic Fault Simulation. Functional Scan-Out.

At-Speed Scan (AC) Test Goals.

AC Test Goals. Cost Drivers.

At-Speed Scan Testing.

Uses of At-Speed Scan Testing. At-Speed Scan Sequence. At-Speed Scan versus DC Scan.

The At-Speed Scan Architecture.

At-Speed Scan Interface. At-Speed "Safe Shifting" Logic. At-Speed Scan Sample Architecture.

The At-Speed Scan Interface.

At-Speed Scan Shift Interface. At-Speed Scan Sample Interface.

Multiple Clock and Scan Domain Operation.

Multiple Timing Domains.

Scan Insertion and Clock Skew.

Multiple Clock Domains, Clock Skew, and Scan Insertion. Multiple Time Domain Scan Insertion.

Scan Insertion for At-Speed Scan.

Scan Cell Substitution. Scan Control Signal Insertion. Scan Interface Insertion. Other Considerations.

Critical Paths for At-Speed Scan.

Critical Paths. Critical Path Selection. Path Filtering. False Path Content. Real Critical Paths. Critical Path Scan-Based Diagnostics.

Scan-Based Logic BIST.

Pseudo-Random Pattern Generation. Signature Analysis. Logic Built-In Self-Test. LFSR Science (A Quick Tutorial). X-Management. Abasing.

Scan Test Fundamentals Summary. Recommended Reading.



4. Memory Test Architectures and Techniques.

Introduction to Memory Testing.

Purpose. Introduction to Memory Test.

Types of Memories.

Categorizing Memory Types.

Memory Organization.

Types of Memory Organization.

Memory Design Concerns.

Trade-Offs in Memory Design.

Memory Integration Concerns.

Key Issues in Memory Integration.

Embedded Memory Testing Methods.

Memory Test Methods and Options.

The Basic Memory Testing Model.

Memory Testing. Memory Test Fault Model. Memory Test Failure Modes.

The Stuck-At Bit-Cell Based Fault Models.

Stuck-At Based Memory Bit-Cell Fault Models. Stuck-At Fault Exercising and Detection.

The Bridging Defect-Based Fault Models.

Bridging Defect-Based Memory Test Fault Models. Linking Defect Memory Test Fault Models. Bridging Fault Exercising and Detection.

The Decode Fault Model.

Memory Decode Fault Models. Decode Fault Exercising and Detection.

The Data Retention Fault.

Memory Test Data Retention Fault Models. DRAM Refresh Requirements.

Diagnostic Bit Mapping.

Memory Test Diagnostics: Bit Mapping.

Algorithmic Test Generation.

Introduction to Algorithmic Test Generation. Automatic Test Generation. BIST-Based Algorithmic Testing.

Memory Interaction with Scan Testing.

Scan Test Considerations. Memory Interaction Methods. Input Observation. Output Control.

Scan Test Memory Modeling.

Modeling the Memory for ATPG Purposes. Limitations.

Scan Test Memory Black-Boxing.

The Memory Black-Boxing Technique. Limitations and Concerns.

Scan Test Memory Transparency.

The Memory Transparency Technique. Limitations and Concerns.

Scan Test Memory Model of The Fake Word.

The Fake Word Technique. Limitations and Concerns.

Memory Test Requirements for MBIST.

Memory Test Organization.

Memory Built-In Self-Test Requirements.

Overview of Memory BIST Requirements. At-Speed Operation.

An Example Memory BIST.

A Memory Built-In Self-Test. Optional Operations. An Example Memory Built-In Self-Test.

MBIST Chip Integration Issues.

Integrating Memory BIST.

MBIST Integration Concerns.

MBIST Default Operation.

MBIST Power Concerns.

Banked Operation.

MBIST Design-Using LFSRs.

Pseudo-Random Pattern Generation for Memory Testing. Signature Analysis and Memory Testing. Signature Analysis and Diagnostics.

Shift-Based Memory BIST.

Shift-Based Memory Testing. Output Assessment.

ROM BIST.

Purpose and Function of ROM BIST. The ROM BIST Algorithm. ROM MISR Selection. Signature Compare Method.

Memory Test Summary. Recommended Reading.



5. Embedded Core Test Fundamentals.

Introduction to Embedded Core Testing.

Purpose. Introduction to Embedded Core-Based Chip Testing. Reuse Cores. Chip Assembly Using Reuse Cores.

What Is a Core?

Defining Cores. The Core DFT and Test Problem. Built-In DFT.

What is Core-Based Design?

Design of a Core-Based Chip. Core-Based Design Fundamentals.

Reuse Core Deliverables.

Embedded Core Deliverables.

Core DFT Issues.

Embedded Core-Based Design Test Issues.

Development of a Reusable Core.

Embedded Core Considerations for DFT.

DFT Interface Considerations-Test Signals.

Embedded Core Interface Considerations for DFT-Test Signals.

Core DFT Interface Concerns-Test Access.

Test Access to the Core Interface.

DFT Interface Concerns-Test Wrappers.

The Test Wrapper as a Signal reduction Element. The Test Wrapper as a Frequency Interface. The Test Wrapper as a Virtual Test Socket.

The Registered Isolation Test Wrapper. The Slice Isolation Test Wrapper. The Isolation Test Wrapper-Slice Cell. The Isolation Test Wrapper-Core DFT Interface. Core Test Mode Default Values.

Internal versus External Test Quiescence Defaults Application.

DFT Interface Wrapper Concerns.

Lack of Bidirectional Signals. Test Clock Source Considerations.

DFT Interface Concerns-Test Frequency.

Embedded Core Interface Concerns for DFT-Test Frequency. Solving the Frequency Problem.

Core DFT Development.

Internal Parallel Scan. Wrapper Parallel Scan. Embedded Memory BIST. Other DFT Features.

Core Test Economics.

Core DFT, Vectors, and Test Economics. Core Selection with Consideration to DFT Economics.

Chip Design with a Core.

Elements of a Core-Based Chip. Embedded Core Integration Concerns. Chip-Level DFT.

Scan Testing the Isolated Core. Scan Testing the Non-Core Logic.

Scan Testing the Non-Core Logic in Isolation. Chip-Level Testing and Tester Edge Sets.

User Defined Logic Chip-Level DFT Concerns. Memory Testing with BIST. Chip-Level DFT Integration Requirements.

Embedded Core-Based DFT Integration Architecture. Physical Concerns.

Embedded Test Programs. Selecting or Receiving a Core. Embedded Core DFT Summary. Recommended Reading.



About the CD.


Glossary of Term.


Index.

商品描述(中文翻譯)

描述：


8482G-5


來自業界內部人士的第一本實用 DFT 指導書。

跳過高深的理論和數學公式—直接進入數位設計和測試的實務，了解在現實世界中如何運作。學習針對當今商業需求的實用測試策略，這些需求包括品質、可靠性和成本控制，並在典型高壓生產環境的緊迫期限內工作。針對數位 IC 和嵌入式核心系統的測試設計（Design-for-Test）幫助您在矽晶圓面積、操作頻率和功耗等資源之間優化工程權衡，同時平衡企業對測試成本、上市時間和產量時間的關注。您還將透過專注於自動測試模式生成（Automatic Test Pattern Generation, ATPG）來提升效率。

本書包含一個路線圖，讓您可以微調學習進度，若想直接跳到特定主題。主要主題包括：


  • 基於核心的設計，專注於嵌入式核心和嵌入式記憶體

  • 系統單晶片和超大規模集成設計問題

  • AC 掃描、速度掃描和嵌入式 DFT

  • 內建自我測試，包括記憶體 BIST、邏輯 BIST 和掃描 BIST

  • 虛擬測試插座和隔離測試

  • 可重用設計，包括可重用向量和核心

  • VSIA 和 IEEE P1500 標準所解決的測試問題


針對數位 IC 和嵌入式核心系統的測試設計充滿了直接來自作者教學材料的全頁圖形。每個部分都用流程圖、工程圖和概念摘要進行說明，使學習和參考變得快速而簡單。本書是參與設計和測試的工程師和管理者的必備之作。

隨附的 CD-ROM 包含所有書中插圖的全彩版本，格式為 Acrobat PDF。這些圖像可以在螢幕上互動查看或列印出來以製作教學用的投影片。隨書附贈的 Acrobat Reader 軟體適用於 Windows 和 UNIX 電腦。


 


目錄：


前言。


致謝。


導言。



1. 測試和測試設計基礎。



測試和 DFT 基礎介紹。



目的。測試、測試過程和測試設計的介紹。並行測試工程。



測試的原因。



為什麼要測試？為什麼要添加測試邏輯？DFT 的利弊看法。



測試的定義。



什麼是測試？刺激。響應。



測試測量標準。



測量什麼？故障度量數學。



故障建模。



物理缺陷。故障建模。



測試類型。



功能測試。結構測試。組合性徹底測試和偽徹底測試。完全徹底測試。測試風格。



製造測試。



製造測試過程。製造測試負載板。製造測試程序。



使用自動測試設備。



自動測試設備。ATE 限制。ATE 成本考量。



測試和引腳時序。



測試儀和設備引腳時序。測試儀邊緣集。測試儀精度和準確性。



製造測試程序組件。



測試程序的組成部分。測試程序優化。



推薦閱讀。




2. 自動測試模式生成基礎。



自動測試模式生成介紹。



目的。自動測試模式生成的介紹。向量生成過程流程。



ATPG 的原因。



為什麼 ATPG？ATPG 的利弊看法。



自動測試模式生成過程。



ATPG 介紹。



介紹組合性卡住故障。



組合性卡住故障。組合性卡住故障檢測。



介紹延遲故障。



延遲故障。延遲故障檢測。



介紹基於電流的故障。



基於電流的測試。基於電流的測試檢測。



可測試性和故障分析方法。



為什麼要進行 ATPG 分析或可測試性分析？有哪些可測試性分析類型？故障有效電路。可控性-可觀察性分析。電路學習。



故障遮蔽。



故障遮蔽的原因和影響。各種故障模型上的故障遮蔽。



卡住故障等價。



故障等價優化。故障等價的副作用。



卡住 ATPG。



故障選擇。執行故障。檢測路徑敏感化。



過渡延遲故障 ATPG。



使用 ATPG 處理過渡延遲故障。過渡延遲是一種粗略的延遲故障。



路徑延遲故障 ATPG。



路徑延遲 ATPG。穩健的故障檢測。路徑延遲設計描述。路徑枚舉。



基於電流的故障 ATPG。



基於電流的 ATPG 演算法。



組合 ATPG 與序列 ATPG。



多循環序列測試模式生成。多時間框架組合 ATPG。兩時間框架 ATPG 限制。基於循環的 ATPG 限制。



向量模擬。



故障模擬。製造測試的模擬。



ATPG 向量。



向量格式。向量壓縮和壓縮。



基於 ATPG 的設計規則。



ATPG 工具的「不」規則清單。規則的例外。



選擇 ATPG 工具。



可測量的項目。ATPG 基準過程。



ATPG 基礎總結。



建立 ATPG 方法論。



推薦閱讀。




3. 掃描架構和技術。



掃描基礎測試介紹。



目的。測試問題。掃描測試。掃描測試的誤解。



功能測試。掃描有效電路。Mux-D 風格掃描觸發器。



多路複用-D 觸發器掃描單元。Mux-D 掃描觸發器的矽晶圓影響。其他類型的掃描觸發器。混合掃描風格。



首選 Mux-D 掃描觸發器。



多路複用-D 觸發器掃描單元的操作優先級。Mux-D 觸發器系列。



掃描移位寄存器或掃描鏈。



測試的掃描架構。掃描移位寄存器（又名掃描鏈）。



掃描單元操作。



掃描單元轉移函數。



掃描測試序列。掃描測試時序。安全掃描移位。安全掃描取樣：無爭用向量。



無爭用向量。



部分掃描。



使用部分掃描的掃描測試。序列 ATPG。



多個掃描鏈。



多個掃描鏈的優勢。平衡掃描鏈。



借用掃描介面。



設置借用掃描介面。共享掃描輸入介面。共享掃描輸出介面。



時鐘、片上時鐘源和掃描。



片上時鐘源和掃描測試。片上時鐘和被掃描測試。



掃描基礎設計規則。



掃描基礎 DFT 和設計規則。規則。



卡住（DC）掃描插入。



DC 掃描插入。附加項。DC 掃描插入和多個時鐘域。



卡住掃描診斷。



實施卡住掃描診斷。診斷故障模擬。功能掃描輸出。



速度掃描（AC）測試目標。



AC 測試目標。成本驅動因素。



速度掃描測試。



速度掃描測試的用途。速度掃描序列。速度掃描與 DC 掃描。



速度掃描架構。



速度掃描架構。

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