Testing of Digital Systems (Hardcover)

N. K. Jha, S. Gupta

  • 出版商: Cambridge
  • 出版日期: 2003-08-05
  • 售價: $7,690
  • 貴賓價: 9.5$7,306
  • 語言: 英文
  • 頁數: 1016
  • 裝訂: Hardcover
  • ISBN: 0521773563
  • ISBN-13: 9780521773560
  • 下單後立即進貨 (約1週~2週)





Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.


Table of Contents

1. Introduction; 2. Fault models; 3. Combinational logic and fault simulation; 4. Test generation for combinational circuits; 5. Sequential ATPG; 6. IDDQ testing; 7. Functional testing; 8. Delay fault testing; 9. CMOS testing; 10. Fault diagnosis; 11. Design for testability; 12. Built-in self-test; 13. Synthesis for testability; 14. Memory testing; 15. High-level test synthesis; 16. System-on-a-chip testing; Index.