Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute (Hardcover)

John Williams

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商品描述

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.

In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.

Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.

A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.

Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.

商品描述(中文翻譯)

這本獨特的教科書以一個VLSI IC設計專案的步驟式學習課程結構為基礎。

在一個預計12週、每週兩天、每天約10小時的時間表中,全面介紹了Verilog語言的基礎知識,以及完成一個包含可合成的PLL的完整70,000個晶體管的全雙工序列化器-解序器所需的一切。

《使用Verilog進行數位VLSI設計》是工程師深入理解Verilog語言所需的全部內容:語法、合成語義、模擬和測試。書中附帶的CD-ROM提供了27個實驗的完整解答。對於有適當電子設計工具的讀者,所有解答都可以按照書中的描述進行開發、模擬和合成。

設計主題的部分列表包括設計分割、層次分解、安全編碼風格、反向註釋、封裝模塊、並行性、競爭條件、基於斷言的驗證、時鐘同步和測試設計。

具體設備的涵蓋範圍包括對觸發器、鎖存器、組合邏輯、多路器、計數器、移位寄存器、解碼器、狀態機、記憶體(包括奇偶校驗和ECC)、FIFO和PLL的基本討論和練習。還介紹了Verilog的指定區塊,包括其路徑延遲和時序檢查。