RISC-V System-on-Chip Design (Paperback)
暫譯: RISC-V 系統單晶片設計 (平裝本)
Harris, David, Stine, James, Harris, Sarah
- 出版商: Morgan Kaufmann
- 出版日期: 2026-07-01
- 售價: $4,450
- 貴賓價: 9.5 折 $4,227
- 語言: 英文
- 頁數: 856
- 裝訂: Quality Paper - also called trade paper
- ISBN: 0323994989
- ISBN-13: 9780323994989
-
相關分類:
RISC-V、Computer-architecture、VLSI
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商品描述
RISC-V System-On-Chip Design fits at the nexus of computer architecture, microarchitecture, and chip design. It is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and high school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.
It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.
Ancillary materials include a GitHub repository with complete open-source SystemVerilog code for the fully-functional Wally RISC-V SoC, validation code in C and assembly language, code for benchmarking and booting Linux, labs, slides, exercises, and figures.
Please note that chapters 20-23 and Appendices A-D and F are not included in the print book but are available on the Companion Site at
https://shop.elsevier.com/books/book-companion/9780323994989. These chapters and appendices are also in the electronic version of the book.
Supplementary resources for the book are also available on a website hosted by the authors at: ddcabook.com.
- Includes a concrete application & implementation of the open RISC-V architecture
- Explores rarely taught microarchitectural issues:
- Pipelines, buses, caches, branch prediction, virtual memory, floating-point, cryptography & peripherals
- Illustrates system design with CORE-V Wally, a fully functional RISC-V system-on-chip:
- Programming & debugging RISC-V in C & assembly
- SystemVerilog design, debug, verification & synthesis
- Benchmarking
- Booting Linux on a simulator & FPGA
- Provides complete open-source code: github.com/openhwgroup/cvw
商品描述(中文翻譯)
RISC-V System-on-Chip 設計位於電腦架構、微架構與晶片設計的交會點。本書以具備有限相關背景知識的高年級大學生為對象,力求深入淺出。書中會在必要時說明作業系統、VLSI 與記憶體系統的相關概念;對大多數章節而言,高中數學程度即足以應付。不過,浮點數與除法等章節主要適合對電腦算術感到好奇的讀者。如同 Harris 與 Harris 合著的 Digital Design and Computer Architecture 教科書,本書透過易於閱讀且完整的說明、側欄補充內容,以及偶爾穿插的幽默與漫畫,吸引學生閱讀。
本書隨附一套開放原始碼實作,並提供各章末的習題,讓讀者以不同方式擴充 RISC-V 處理器。輔助教材包括一個 GitHub 儲存庫,其中提供完整的開放原始碼 SystemVerilog 程式碼、以 C 與組合語言撰寫的驗證程式碼,以及用於效能評測與啟動 Linux 的程式碼。
輔助教材還包括一個 GitHub 儲存庫,其中提供功能完整的 Wally RISC-V SoC 的完整開放原始碼 SystemVerilog 程式碼、以 C 與組合語言撰寫的驗證程式碼、用於效能評測與啟動 Linux 的程式碼、實驗、投影片、練習題與圖表。
請注意,Chapter 20–23 以及 Appendices A–D 和 F 未收錄於印刷版書籍中,但可於 Companion Site 取得:
https://shop.elsevier.com/books/book-companion/9780323994989
這些章節與附錄也收錄於本書的電子版本中。
本書的補充資源亦可於作者維護的網站取得:
ddcabook.com
• 收錄開放式 RISC-V 架構的具體應用與實作
• 探討較少在教學中介紹的微架構議題:
• 管線、匯流排、快取、分支預測、虛擬記憶體、浮點運算、密碼學與周邊裝置
• 透過功能完整的 RISC-V system-on-chip CORE-V Wally 說明系統設計:
• 使用 C 與組合語言進行 RISC-V 程式設計與除錯
• SystemVerilog 設計、除錯、驗證與合成
• 效能評測
• 在模擬器與 FPGA 上啟動 Linux
• 提供完整的開放原始碼:
github.com/openhwgroup/cvw
作者簡介
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.
James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library.
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing.
Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.
Rose Thompson is a processor architect at Skyworks Solutions, Inc. She received her Ph.D. in Electrical Engineering from Oklahoma State University and two B.S. degrees in Electrical Engineering and Computer Engineering from the University of Washington. She has also designed chips at the Air Force Research Laboratory. Her professional interests include SoC design and verification, custom instruction set architectures, branch prediction, memory systems, and secure computing. Rose also enjoys biking, hiking, rock climbing, and playing the piano.
作者簡介(中文翻譯)
David Harris 是 Harvey Mudd College 的 Harvey S. Mudd 工程設計講座教授。他於 Stanford University 取得電機工程博士學位,並於 MIT 取得電機工程與電腦科學碩士學位。在 Stanford University 就讀之前,他曾任職於 Intel,擔任 Itanium 與 Pentium II 處理器的邏輯與電路設計師。此後,他曾為 Sun Microsystems、Hewlett-Packard、Broadcom 及其他設計公司提供顧問服務。David 擁有十多項專利,除了著有三本其他晶片設計教科書外,也撰寫了許多南加州健行指南。工作之餘,他喜歡健行、飛行,以及和三個兒子一起動手製作各種物品。
James Stine 是 Oklahoma State University 的 Edward Joullian 工程學講座教授。他的研究領域包括電腦算術、記憶體架構,以及電子設計自動化(Electronic Design Automation, EDA)設計流程。他著有許多探討電腦算術應用之架構最佳化,以及記憶體架構介接的論文。他著有三本書:Digital Datapath Computer Arithmetic with Verilog、Adder Architectures for VLSI Implementations,以及 System on Chip Design Flow and Standard-Cell Library。
Sarah L. Harris 是 Harvey Mudd College 的工程學助理教授。她於 Stanford University 取得電機工程博士與碩士學位。在 Stanford University 就讀之前,她於 Brigham Young University 取得電機與電腦工程學士學位。Sarah 也曾與 Hewlett-Packard、San Diego Supercomputer Center、Nvidia,以及位於北京的 Microsoft Research 合作。
Sarah 熱愛教學、探索與開發新技術、旅行、風浪板、攀岩,以及彈奏吉他。她近期的經歷包括研究用於數位電路設計的草圖介面、擔任 National Public Radio 附屬電台的科學記者,以及學習風箏衝浪。她會說四種語言,並期待在不久的將來學習更多語言。
Rose Thompson 是 Skyworks Solutions, Inc. 的處理器架構師。她於 Oklahoma State University 取得電機工程博士學位,並於 University of Washington 取得電機工程與電腦工程兩個學士學位。她也曾在 Air Force Research Laboratory 設計晶片。她的專業興趣包括 SoC 設計與驗證、自訂指令集架構、分支預測、記憶體系統,以及安全運算。Rose 也喜歡騎自行車、健行、攀岩,以及彈奏鋼琴。