Writing Testbenches using SystemVerilog (Hardcover)
暫譯: 使用 SystemVerilog 撰寫測試平台 (精裝版)

Description

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.

Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.

Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.

Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.

Written for:

Design automation verification engineers

 

What is Verification?.- Verification Technologies.- The Verification Plan.- High-Level Modeling.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.- Appendix A: Coding Guidelines.- Appendix B: Glossary.