Digital Design Using Veriloghdl: VLSI Modeling, Coding and Verification
暫譯: 使用Verilog HDL的數位設計：VLSI建模、編碼與驗證

Digital Design using VerilogHDL: VLSI Modeling, Coding and Verification covers the concepts of digital logic design, including, logic simplification and optimization for digital circuit synthesis and implementation, design and integration of logics (combinational and sequential) in the building of digital circuits and systems, the practical aspects of number systems, the use of VerilogHDL in the logic design, testbench verification, and the synthesis of digital circuits and systems with HDL code examples. Users will find an approach to the design, integration, verification, and synthesizing of a digital logic circuit, complete with coding examples.