Design Through Verilog HDL (Hardcover)

T. R. Padmanabhan, B. Bala Tripura Sundari

  • 出版商: Wiley
  • 出版日期: 2003-11-05
  • 售價: $5,910
  • 貴賓價: 9.5$5,615
  • 語言: 英文
  • 頁數: 472
  • 裝訂: Hardcover
  • ISBN: 0471441481
  • ISBN-13: 9780471441489
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)





A comprehensive resource on Verilog HDL for beginners and experts

Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.

Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include:

  • Primitives
  • Gate and Net delays
  • Buffers
  • CMOS switches
  • State machine design

Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book s final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.

Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource. 

Table of Contents

Introduction to VLSI Design.

Introduction to VERILOG.

Language Constructs and Conventions in VERILOG.

Gate Level Modeling-1.

Gate Level Modeling-2.

Modeling at Data Flow Level.

Behavioral Modeling-1.

Behavioral Modeling-2.

Functions, Tasks, and User-Defined Primitives.

Switch Level Modeling.

System Tasks, Functions, and Compiler Directives.

Queues, PLAs, and FSMS.

Appendix A: Keywords and their Significance.

Appendix B: Truth Tables of Gates and Switches.