Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors [Hardcover]

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

這本書全面描述了從簡單的順序短流水線設計到超級標量的無序處理器的架構。它討論了以下主題：
- 無序處理所需的策略和機制，如寄存器重命名、保留站和重排序緩衝區
- 高性能優化，如分支預測器、指令調度和載入存儲推測
- 在單個和多個處理器的高速緩存層次結構中容忍延遲的設計選擇和增強
- 最先進的多線程和多處理器，強調單芯片實現
這些主題以概念性思想呈現，如果適用的話，還有評估性能影響的指標和實現示例。重點是黑盒和算法級別的工作原理。作者還提供了足夠的詳細信息，以便讀者能夠理解設計特性如何提高性能以及複雜性的註冊轉移級別。