Digital Systems Design Using VHDL
暫譯: 使用 VHDL 的數位系統設計

Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design in Chapter 1, the author introduces the basics of VHDL in Chapter 2, and then incorporates more coverage of VHDL topics as needed, with advanced topics covered in Chapter 8. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process. For example, in Chapter 9, the author develops VHDL models for a RAM memory and a microprocessor bus interface; he then uses a VHDL simulation to verify that timing specifications for the interface between the memory and microprocessor bus are satisfied. The book also covers the use of CAD tools to synthesize digital logic from a VHDL description (in Chapter 8), and stresses the use of programmable logic devices, including programmable gate arrays. Chapter 10 introduces methods for testing digital systems including boundary scan and a built-in self-test.