VHDL Coding Styles and Methodologies, 2/e (Hardcover)

VHDL Coding Styles and Methodologies, Second Edition is a follow-up book to the first edition of the same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy-to-read book that gave in-depth coverage of both the language and coding methodologies. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity is kindly making available an evaluation version of Synplify, a very efficient, user-friendly and easy-to-use FPGA synthesis tool. Synplify provides a user with both the RTL and gate-level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool. VHDL Coding Styles and Methodologies, Second Edition is intended for professional engineers as well as students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, leads the reader in the right direction from the beginning. CD INCLUDED VHDL Coding Styles and Methodologies, Second Edition includes a CD that contains + All code included in the book + GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages + GNU TSHELL tools that emulate Unix shell + Thirty-day evaluation of ModelSim VHDL compiler/simulator from Model Technology + Twenty-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity + VHDL template demonstrating the language syntax + VHDL '87 and VHDL '93 formal syntax in HTML format.

《VHDL編碼風格與方法論，第二版》是第一版同名書籍以及《VHDL常見問題解答》第一版和第二版的續集。本書最初是作為一門VHDL培訓課程的教材而撰寫的。作者開始寫這本書是因為他找不到一本實用且易於閱讀的書籍，能夠深入介紹VHDL語言和編碼方法論。這本新版提供了有關設計測試環境中可重用軟體方法論的實用信息，以及在合成中使用VHDL的指南。書中描述的所有VHDL代碼都在附帶的光碟中，光碟還包括了GNU工具套件，其中包含EMACS語言敏感編輯器（具有VHDL、Verilog和其他語言模板）以及模擬Unix shell的TSHELL工具。Model Technology慷慨地提供了ModelSim的評估版本，這是一個被公認的行業標準VHDL/Verilog編譯器和模擬器，支持方便地查看正在分析的模型以及許多調試功能。此外，Synplicity友好地提供了Synplify的評估版本，這是一個非常高效、用戶友好且易於使用的FPGA綜合工具。Synplify提供了合成模型的RTL和閘級視圖，以及設計的性能報告。工具中還提供了優化機制。

《VHDL編碼風格與方法論，第二版》適用於專業工程師和學生。它分為十三章，每章涵蓋語言的不同方面，並提供完整的示例。它提供了一種實用的學習VHDL的方法。結合方法論和編碼風格以及VHDL規則，從一開始就引導讀者朝著正確的方向前進。

附帶光碟：
- 包含書中的所有代碼
- GNU EMACS語言敏感編輯器，具有VHDL、Verilog和其他語言的模板
- 模擬Unix shell的GNU TSHELL工具
- Model Technology提供的30天評估版ModelSim VHDL編譯器/模擬器
- Synplicity提供的20天評估版Synplify VHDL/Verilog FPGA綜合器
- 展示語言語法的VHDL模板
- VHDL '87和VHDL '93的正式語法以HTML格式呈現。