Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog)(Paperback)
暫譯: 硬體中的有限狀態機:理論與設計(使用 VHDL 和 SystemVerilog)(平裝本)

Pedroni, Volnei A.

  • 出版商: MIT
  • 出版日期: 2025-05-27
  • 售價: $2,080
  • 貴賓價: 9.5$1,976
  • 語言: 英文
  • 頁數: 352
  • 裝訂: Quality Paper - also called trade paper
  • ISBN: 0262052903
  • ISBN-13: 9780262052900
  • 相關分類: Verilog
  • 海外代購書籍(需單獨結帳)

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商品描述

A comprehensive guide to the theory and design of hardware-implemented finite state machines, with design examples developed in both VHDL and SystemVerilog languages.

Modern, complex digital systems invariably include hardware-implemented finite state machines. The correct design of such parts is crucial for attaining proper system performance. This book offers detailed, comprehensive coverage of the theory and design for any category of hardware-implemented finite state machines. It describes crucial design problems that lead to incorrect or far from optimal implementation and provides examples of finite state machines developed in both VHDL and SystemVerilog (the successor of Verilog) hardware description languages.

Important features include: extensive review of design practices for sequential digital circuits; a new division of all state machines into three hardware-based categories, encompassing all possible situations, with numerous practical examples provided in all three categories; the presentation of complete designs, with detailed VHDL and SystemVerilog codes, comments, and simulation results, all tested in FPGA devices; and exercise examples, all of which can be synthesized, simulated, and physically implemented in FPGA boards. Additional material is available on the book's Website.

Designing a state machine in hardware is more complex than designing it in software. Although interest in hardware for finite state machines has grown dramatically in recent years, there is no comprehensive treatment of the subject. This book offers the most detailed coverage of finite state machines available. It will be essential for industrial designers of digital systems and for students of electrical engineering and computer science.

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作者簡介

Volnei A. Pedroni is Professor Emeritus in the Electronics Engineering Department at Brazil's Federal University of Technology, UTFPR, and a regular Visiting Professor of Electrical Engineering at the California Institute of Technology. Dr. Pedroni's MSc and PhD degrees are both from Caltech. He is the author of Finite State Machines in Hardware: Theory and Design (with VHDL and SystemVerilog) (MIT Press).

作者簡介(中文翻譯)

Volnei A. Pedroni 是巴西聯邦科技大學 (UTFPR) 電子工程系的名譽教授,同時也是加州理工學院 (Caltech) 電機工程的定期訪問教授。Pedroni 博士的碩士和博士學位均來自加州理工學院。他是《硬體中的有限狀態機:理論與設計(使用 VHDL 和 SystemVerilog)》一書的作者(麻省理工學院出版社)。