The Cache Coherence Problem In Shared-memory Multiprocessors: Software Solutions

Igor Tartalja, Veljko Milutinović

  • 出版商: Wiley
  • 出版日期: 1996-02-13
  • 售價: $3,320
  • 貴賓價: 9.5$3,154
  • 語言: 英文
  • 頁數: 358
  • 裝訂: Paperback
  • ISBN: 0818670967
  • ISBN-13: 9780818670961
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Almost all software solutions are developed through academic research and implemented only in prototype machines leaving the field of software techniques for maintaining the cache coherence widely open for future research and development. This book is a collection of all the representative approaches to software coherence maintenance including a number of related efforts in the performance evaluation field.

The book presents a selection of 27 papers dealing with state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a set of four introductory readings that provides a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and illustrates static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.

The book is intended for the experienced reader in computer engineering but possibly a novice in the topic of cache coherence. It also provides an in-depth understanding of the problem as well as a comprehensive overview for multicomputer designers, computer architects, and compiler writers. In addition, it is a software coherence reference handbook for advanced undergraduate and typical graduate students in multiprocessing and multiprogramming areas.


Table of Contents:



Chapter 1: Introductory Readings.

How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs (L. Lamport).

Synchronization, Coherence, and Event Ordering in Multiprocessors (M. Dubois, C. Scheurich, and F.A. Briggs).

Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons (D. Lilja).

Software Cache Consistency in Shared-Memory Multiprocessors: A Survey of Approaches and Performance Evaluation Studies (I. Tartalja and V. Milutinović).

Chapter 2: Static Software Cache Coherence Schemes.

Compiler-Directed Cache Management in Multiprocessors (H. Cheong and A.V. Veidenbaum).

RP3 Processor-Memory Element (W.C. Brantley, K.P. McAuliffe, and J. Weiss).

A Compiler-Assisted Cache Coherence Solution for Multiprocessors (A.V. Veidenbaum).

A Cache Coherence Scheme With Fast Selective Invalidation (H. Cheong and A.V. Veidenbaum).

Automatic Management of Programmable Caches (R. Cytron, S. Karlovsky, and K.P. McAuliffe).

A Version Control Approach to Cache Coherence (H. Cheong and A.V. Veidenbaum).

Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps (S.L. Min and J.-L. Baer).

A Generational Algorithm to Multiprocessor Cache Coherence (T.C. Chiueh).

Cache Coherence Using Local Knowledge (E. Darnell and K. Kennedy).

Chapter 3: Dynamic Software Cache Coherence Schemes.

Software-Controlled Caches in the VMP Multiprocessor (D.R. Cheriton, G.A. Slavenburg, and P.D. Boyle).

CPU Cache Consistency with Software Support and Using "One Time Identifiers" (A.J. Smith).

An Approach to Dynamic Software Cache Consistency Maintenance Based on Conditional Invalidation (I. Tartalja and V. Milutinović).

Adaptive Software Cache Management for Distributed Shared Memory Architectures (J.K. Bennett, J.B. Carter, and W. Zwaenepoel).

Chapter 4: Techniques for Modeling and Performance Evaluation of Cache Memories and Cache Coherence Maintenance Mechanisms.

Analysis of Multiprocessors with Private Cache Memories (J.H. Patel).

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories (F.A. Briggs and M. Dubois).

On the Validity of Trace-Driven Simulation for Multiprocessors (E.J. Koldinger, S.J. Eggers, and H.M. Levy).

Multiprocessor Cache Simulation Using Hardware Collected Address Traces (A.W. Wilson).

Cache Invalidation Patterns in Shared-Memory Multiprocessors (A. Gupta and W.-D. Weber).

Benchmark Characterization for Experimental System Evaluation (T.M. Conte and W.W. Hwu).

A Model of Workloads and Its Use in Miss-Rate Prediction for Fully Associative Caches (J.P. Singh. H.S. Stone, and D.F. Thiebaut).

Chapter 5: Performance Evaluation Studies of Software Coherence Schemes).

A Performance Comparison of Directory-Based and Timestamp-Based Cache Coherence Schemes (S.L. Min and J.-L. Baer).

Evaluating the Performance of Software Cache Coherence (S. Owicki and A. Agarwal).

Comparison of Hardware and Software Cache Coherence Schemes (S.V. Adve, V.S. Adve, M.D. Hill, and M.K. Vernon).

About the Author.





如何製作一台正確執行多處理程序的多處理器計算機(L. Lamport)。
多處理器中的同步、一致性和事件排序(M. Dubois、C. Scheurich和F.A. Briggs)。
大規模共享內存多處理器中的快取一致性:問題和比較(D. Lilja)。
共享內存多處理器中的軟體快取一致性:方法和性能評估研究概述(I. Tartalja和V. Milutinović)。
多處理器中的編譯器指導快取管理(H. Cheong和A.V. Veidenbaum)。
RP3處理器-內存元件(W.C. Brantley、K.P. McAuliffe和J. Weiss)。

編譯器輔助的多處理器快取一致性解決方案(A.V. Veidenbaum)。
具有快速選擇性失效的快取一致性方案(H. Cheong和A.V. Veidenbaum)。
可編程快取的自動管理(R. Cytron、S. Karlovsky和K.P. McAuliffe)。
快取一致性的版本控制方法(H. Cheong和A.V. Veidenbaum)。
基於時鐘和時間戳的可擴展快取一致性方案的設計和分析(S.L. Min和J.-L. Baer)。
多處理器快取一致性的世代算法(T.C. Chiueh)。
使用本地知識的快取一致性(E. Darnell和K. Kennedy)。
VMP多處理器中的軟體控制快取(D.R. Cheriton、G.A. Slavenburg和P.D. Boyle)。
具有軟體支持和使用“一次性標識符”的CPU快取一致性(A.J. Smith)。
基於條件失效的動態軟體快取一致性維護方法(I. Tartalja和V. Milutinović)。