Writing Testbenches: Functional Verification of HDL Models, 2/e (Hardocver)
Janick Bergeron
- 出版商: Springer
- 出版日期: 2003-02-28
- 售價: $1,150
- 貴賓價: 9.5 折 $1,093
- 語言: 英文
- 頁數: 478
- 裝訂: Hardcover
- ISBN: 1402074018
- ISBN-13: 9781402074011
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商品描述
The Second Edition of Writing
Testbenches, Functional Verification of HDL Models presents
the latest verification techniques to produce fully functional first silicon
ASICs, systems-on-a-chip (SoC), boards and entire systems.
From the Foreword:
Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc.
Topics included in the new Second Edition:
From the Foreword:
Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc.
Topics included in the new Second Edition:
- Discussions on OpenVera and e;
- approaches for writing constrainable random stimulus generators;
- strategies for making testbenches self-checking;
- a clear blueprint of a verification process that aims for first time success;
- recent advances in functional verification such as coverage-driven verification process;
- VHDL and Verilog language semantics;
- the semantics are presented in new verification-oriented languages
- techniques for applying stimulus and monitoring the response of a design;
- behavioral modeling using non-synthesizeable constructs and coding style;
- updated for Verilog 2001.
Contents：
About the Cover. Foreword. Preface. Why This Book Is Important. What This Book Is About. What Prior Knowledge You Should Have. Reading Paths. Choosing a Language: VHDL vs. Verilog. Hardware Verification Languages. And the Winner is... For More Information. Acknowledgements.
- 1: What is Verification? What is a Testbench? The Importance of Verification. Reconvergence Model. The Human Factor. What Is Being Verified? Functional Verification Approaches. Testing Versus Verification. Design and Verification Reuse. The Cost of Verification. Summary.
- 2: Verification Tools. Linting Tools. Simulators. Verification Intellectual Property. Waveform Viewers. Code Coverage. Functional Coverage. Verification Languages. Assertions. Revision Control. Issue Tracking. Metrics. Summary.
- 3: The Verification Plan. The Role of the Verification Plan. Levels of Verification. Verification Strategies. From Specification to Features. Directed Testbenches Approach. Coverage-Driven Random-Based Approach. Summary.
- 4: High-Level Modeling. Behavioral versus RTL Thinking. You Gotta Have Style! Structure of Behavioral Code. Data Abstraction. Object-Oriented Programming. Aspect-Oriented Programming. The Parallel Simulation Engine. Race Conditions. Verilog Portability Issues. Summary.
- 5: Stimulus and Response. Reference Signals. Simple Stimulus. Simple Output. Complex Stimulus. Bus-Functional Models. Response Monitors. Transaction-Level Interface. Summary.
- 6: Architecting Testbenches. Test Harness. VHDL Test Harness. Design Configuration. Self-Checking Testbenches. Directed Stimulus. Random Stimulus. Summary.
- 7: Simulation Management. Behavioral Models. Pass or Fail? Managing Simulations. Regression. Summary.
- APPENDIX A: Coding Guidelines. Directory Structure. General Coding Guidelines. Naming Guidelines. HDL Coding Guidelines.
- APPENDIX B: Glossary. Afterwords. Index.