Logic Synthesis and Verification Algorithms
暫譯: 邏輯合成與驗證演算法
Hachtel, Gary D., Somenzi, Fabio
- 出版商: Springer
- 出版日期: 2013-03-18
- 售價: $4,140
- 貴賓價: 9.5 折 $3,933
- 語言: 英文
- 頁數: 564
- 裝訂: Quality Paper - also called trade paper
- ISBN: 1475770367
- ISBN-13: 9781475770360
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相關分類:
Algorithms-data-structures
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商品描述
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
商品描述(中文翻譯)
《邏輯合成與驗證演算法》是一本為 VLSI 邏輯合成與驗證、設計自動化、計算機輔助設計 (CAD) 及高級離散數學課程而設計的教科書。它同時也作為專業人士和學生在設計自動化領域的基本參考書籍。《邏輯合成與驗證演算法》探討了 VLSI（超大規模集成電路）的理論基礎。它結合並整合了邏輯合成和形式驗證的現代發展，以及更傳統的開關理論和有限自動機理論的內容。該書還提供了布爾代數和離散數學的背景資料。這本書的一個獨特特點是包含大量已解決的問題。在整本書中，所涵蓋的演算法都是基於使用現有合成程序的一個或多個問題的主題。
