Phase-Locked Loops Engineering Handbook for Integrated Circuits

Stanley J. Goldman

  • 出版商: Artech House
  • 出版日期: 2007-02-28
  • 售價: $7,113
  • 貴賓價: 9.5$6,757
  • 語言: 英文
  • 頁數: 586
  • 裝訂: Hardcover
  • ISBN: 159693154X
  • ISBN-13: 9781596931541

無法訂購

買這商品的人也買了...

相關主題

商品描述

Description:

ICs for microprocessors, DSPs, microcontrollers, and telecommunications are increasingly demanding higher frequencies ranging from 200 to 4000 MHz. Monolithic PLLs can meet these demands, but properly designing new monolithic PLLs is a demanding, complex activity. To guide you through design, simulation, and troubleshooting, turn to this collection of practical solutions, SPICE listings, simulation techniques, and testing set-ups.

Systems designers are requiring that more and more functions be integrated onto a single chip. So you can meet these challenging requirements, this book explains how you can design PLLs so they are isolated from other circuits on a chip, consume minimal power, occupy small die areas, use small value capacitors, and avoid the need for inductors. It gives you all the transistor-level details for designing today's ICs and provides SPICE simulations and methods for verifying performance. This easy-to-reference handbook also thoroughly covers traditional PLL design and development.

 

Table of Contents:

Overview of PLL?General Description. Phase-Locked Loop (PLL) Literature. Loop Classifications.? Example Applications.

System Analysis?Transfer Function and Control Systems. Loop Stability, Bode Plot Analysis. Loop Stability, Root Locus Analysis. Loop Component Synthesis for Charge Pump.

System Requirements?Noise Basics. Phase Noises. Jitter. Time Domain Response and Stability. Acquisition of Lock. Spurious Signals.

Components: Oscillators and Dividers?Dividers. VCOs. Reference Oscillators.

Components: Detectors and Others?Phase Detector. Lock Detectors. Acquisition Aids.

Loop Compensation Synthesis Revisited?Ranking Requirements. Loop Component Synthesis. Active Compensation and Minimum Capacitor Value. Sampling Delay. Fast Switching Time. Minimum Bandwidth. Maximum Bandwidth. Maximum Divide Ratio. Optimum Phase Noise Design.

Test and Measurement?Spurious Signal, Hold in Range, and Lock Range. Step Response. Closed Loop Bandwidth Measurement. Phase Noise Measurements in the Frequency Domain. Jitter Measurements. Test Equipment. Trouble Shooting PLL.

Simulation?SPICE (Transistor Level). Behavioral Model (Block Level). C Programs (Equation Level).

Applications and Extensions?Synthesizer. Clock/Carrier Recovery. Effects of Phase Noise on A/D Converters. All Digital PLLs.

Appendices?Glossary. Symbols.