Phase-Locked Loops Engineering Handbook for Integrated Circuits
暫譯: 集成電路相位鎖定迴路工程手冊

Stanley J. Goldman

Phase-Locked Loops Engineering Handbook for Integrated Circuits
  • 出版商: Artech House Publish
  • 出版日期: 2007-05-22
  • 售價: $7,020
  • 貴賓價: 9.5 折 $6,669
  • 語言: 英文
  • 頁數: 586
  • 裝訂: Hardcover
  • ISBN: 159693154X
  • ISBN-13: 9781596931541

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商品描述

Description:

ICs for microprocessors, DSPs, microcontrollers, and telecommunications are increasingly demanding higher frequencies ranging from 200 to 4000 MHz. Monolithic PLLs can meet these demands, but properly designing new monolithic PLLs is a demanding, complex activity. To guide you through design, simulation, and troubleshooting, turn to this collection of practical solutions, SPICE listings, simulation techniques, and testing set-ups.

Systems designers are requiring that more and more functions be integrated onto a single chip. So you can meet these challenging requirements, this book explains how you can design PLLs so they are isolated from other circuits on a chip, consume minimal power, occupy small die areas, use small value capacitors, and avoid the need for inductors. It gives you all the transistor-level details for designing today's ICs and provides SPICE simulations and methods for verifying performance. This easy-to-reference handbook also thoroughly covers traditional PLL design and development.

 

Table of Contents:

Overview of PLL?General Description. Phase-Locked Loop (PLL) Literature. Loop Classifications.? Example Applications.

System Analysis?Transfer Function and Control Systems. Loop Stability, Bode Plot Analysis. Loop Stability, Root Locus Analysis. Loop Component Synthesis for Charge Pump.

System Requirements?Noise Basics. Phase Noises. Jitter. Time Domain Response and Stability. Acquisition of Lock. Spurious Signals.

Components: Oscillators and Dividers?Dividers. VCOs. Reference Oscillators.

Components: Detectors and Others?Phase Detector. Lock Detectors. Acquisition Aids.

Loop Compensation Synthesis Revisited?Ranking Requirements. Loop Component Synthesis. Active Compensation and Minimum Capacitor Value. Sampling Delay. Fast Switching Time. Minimum Bandwidth. Maximum Bandwidth. Maximum Divide Ratio. Optimum Phase Noise Design.

Test and Measurement?Spurious Signal, Hold in Range, and Lock Range. Step Response. Closed Loop Bandwidth Measurement. Phase Noise Measurements in the Frequency Domain. Jitter Measurements. Test Equipment. Trouble Shooting PLL.

Simulation?SPICE (Transistor Level). Behavioral Model (Block Level). C Programs (Equation Level).

Applications and Extensions?Synthesizer. Clock/Carrier Recovery. Effects of Phase Noise on A/D Converters. All Digital PLLs.

Appendices?Glossary. Symbols.

商品描述(中文翻譯)

描述：
微處理器、數位信號處理器（DSP）、微控制器和電信的集成電路（IC）對於頻率的需求日益增加，範圍從 200 到 4000 MHz。單片相位鎖定迴路（PLL）可以滿足這些需求，但正確設計新的單片 PLL 是一項要求高且複雜的工作。為了指導您進行設計、模擬和故障排除，請參考這本實用解決方案、SPICE 列表、模擬技術和測試設置的集合。

系統設計師要求將越來越多的功能集成到單一晶片上。為了滿足這些挑戰性的要求，本書解釋了如何設計 PLL，使其與晶片上的其他電路隔離，消耗最小的功率，佔用小的晶圓面積，使用小容量的電容器，並避免使用電感器。它提供了設計當今 IC 所需的所有晶體管級細節，並提供 SPICE 模擬和驗證性能的方法。這本易於參考的手冊還徹底涵蓋了傳統 PLL 的設計和開發。

目錄：
PLL 概述？一般描述。相位鎖定迴路（PLL）文獻。迴路分類。示例應用。

系統分析？傳遞函數和控制系統。迴路穩定性，波德圖分析。迴路穩定性，根軌跡分析。充電泵的迴路元件合成。

系統需求？噪聲基礎。相位噪聲。抖動。時域響應和穩定性。鎖定的獲取。雜散信號。

元件：振盪器和分頻器？分頻器。壓控振盪器（VCO）。參考振盪器。

元件：檢測器及其他？相位檢測器。鎖定檢測器。獲取輔助。

迴路補償合成再探討？排名需求。迴路元件合成。主動補償和最小電容值。取樣延遲。快速切換時間。最小帶寬。最大帶寬。最大分頻比。最佳相位噪聲設計。

測試與測量？雜散信號、保持範圍和鎖定範圍。階躍響應。閉迴路帶寬測量。頻域中的相位噪聲測量。抖動測量。測試設備。故障排除 PLL。

模擬？SPICE（晶體管級）。行為模型（區塊級）。C 程式（方程級）。

應用與擴展？合成器。時鐘/載波恢復。相位噪聲對 A/D 轉換器的影響。全數位 PLL。

附錄？術語表。符號。

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