Introduction to Logic Synthesis Using Verilog HDL (Paperback)

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.

《使用Verilog HDL進行邏輯合成入門》解釋了如何撰寫準確的Verilog描述，以便將數位系統合成為具有理想特性的數位系統網表。本書包含了許多Verilog範例，從簡單的組合式網路開始，逐步發展到同步時序邏輯系統。書中還討論了在開發可合成的Verilog HDL時常見的陷阱，以及避免這些陷阱的方法。目標讀者是對數位邏輯原理有基本理解並希望學習如何以Verilog HDL建模數位系統並進行自動合成的任何人。從愛好者和大學本科生到經驗豐富的專業人士，都會發現這是一本引人入勝且易於理解的著作。本書提供了簡潔的內容涵蓋範圍，並包含許多範例，讓讀者能夠快速生成高質量的可合成Verilog模型。