Network Processor Design : Issues and Practices, Volume 2, 2/e (Paperback)

Summary

Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.

Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

Table of Contents

Network Processor Design: Issues and Practics, Volume 2
Contents
Preface
Chapter 1. Network Processors: Themes and Challenges, Patrick Crowley, Mark Franklin, Haldun Hadimioglu, and Peter Z. Onufryk
Part 1. Design Principles
Chapter 2. A Programmable Scalable Platform for Next Generation Networking, Christos J.Georgiou, Valentina Salapura, and Monty Denneau
Chapter 3. Power Considerations in Network Processor Design, Mark A. Franklin and Tilman Wolf
Chapter 4. Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors, Patrick Crowley and Jean-Loup Baer
Chapter 5. Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas, Anand Srinivasan, Philip Holman, James Anderson, Sanjoy Baruah and Jasleen Kaur
Chapter 6. A Massively Multithreaded Packet Processor, Steve Melvin, Mario Nemirovsky, Enric Musoll, Jeff Huynh, Rodolfo Milito, Hector Urdaneta, and Koroush Saraf
Chapter 7. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Matthias Gries, Chidamber Kulkarni, Christian Sauer and Kurt Keutzer
Chapter 8. Packet Classification and Termination in a Protocol Processor, Ulf Nordqvist and Dake Liu
Chapter 9. NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker and Kurt Keutzer
Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors, Gokhan Memik and William H. Mangione-Smith
Chapter 11. Efficient and Faithful Performance Modeling for Network-Processor Based System Designs, Prashant Pradhan, Wen Xu, Indira Nair and Sambit Sahu
Chapter 12. High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200, Roshan K. Thomas, Brian Mark, Tommy Johnson and James Croall
Chapter 13. Directions in Packet Classification for Network Processors, Michael E. Kounavis, Alok Kumar, Harrick Vin, Raj Yavatkar and Andrew T. Campbell
Part 2. Practices
Chapter 14. Implementing High-performance, High-value Traffic Management Using Agere Network Processor Solutions, Jian-Guo Chen, David Sonnier, Robert Munoz, Vinoj Kumar, and Ambalavanar Arulambalam
Chapter 15. AMCC - nPcoreTM "NISC" Architecture, Robin Melnick and Keith Morris
Chapter 16. Adaptable Badwidth Allocation for QoS Support in Network Processors, Clark Jeffries, Mohammad Peyravian, and Ravi Sabhikhi
Chapter 17. IDT - Network Search Engine with QDRTM LA-1 Interface, Michael J. Miller
Chapter 18. Implementing Voice over AAL2 on a Network Processor, Jaroslaw Sydir, Prashant Chandra, Alok Kumar, Sridhar Lakshmanamurthy, Longsong Lin, Muthaiah Venkatachalam
Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor, Pranav Gambhire
Chapter 20. A C-based Programming Language for Multiprocessor Network SoC Architectures. Kevin Crozier

摘要

回應對於性能、靈活性和經濟要求不斷升級的需求，網絡行業選擇圍繞網絡處理器建立產品。為了應對這個新興領域的巨大挑戰，本卷的編輯們創建了第一屆網絡處理器研討會，為科學家和工程師提供了一個討論這些設備的架構、設計、編程和使用的最新研究的論壇。這一系列的卷冊不僅包含了年度研討會的成果，還特別委託了一些突出行業最新網絡處理器的材料。

與前一卷《網絡處理器設計：原理與實踐》一樣，第二卷《網絡處理器設計：問題與實踐》定義並推進了網絡處理器設計領域。第二卷包含了20章，由該領域領先的學術和工業研究人員撰寫，主題涵蓋從架構到編程模型，從安全性到服務質量。

目錄

網絡處理器設計：問題與實踐，第二卷
目錄
前言
第1章 網絡處理器：主題與挑戰，Patrick Crowley、Mark Franklin、Haldun Hadimioglu和Peter Z. Onufryk
第一部分 設計原則
第2章 下一代網絡的可編程可擴展平台，Christos J.Georgiou、Valentina Salapura和Monty Denneau
第3章 網絡處理器設計中的功耗考慮，Mark A. Franklin和Tilman Wolf
第4章 硬件輔助多線程處理器的最壞情況執行時間估計，Patrick Crowley和Jean-Loup Baer
第5章 基於處理器的路由器平台的多處理器調度：問題和思路，Anand Srinivasan、Philip Holman、James Anderson、Sanjoy Baruah和Jasleen Kaur
第6章 大規模多線程封包處理器，Steve Melvin、Mario Nemirovsky、Enric Musoll、Jeff Huynh、Rodolfo Milito、Hector Urdaneta和Koroush Saraf
第7章 探索網絡處理器處理元拓撲的性能和可編程性之間的平衡，Matthias Gries、Chidamber Kulkarni、Christian Sauer和Kurt Keutzer
第8章 協議處理器中的封包分類和終止，Ulf Nordqvist和Dake Liu
第9章 NP-Click：Intel IXP1200的編程模型，Niraj Shah、William Plishker和Kurt Keutzer
第10章 NEPAL：一個為網絡處理器高效結構化應用程序的框架，Gokhan Memik和William H. Mangione-Smith
第11章 面向基於網絡處理器的系統設計的高效和忠實性能建模，Prashant Pradhan、Wen Xu、Indira Nair和Sambit Sahu
第12章 基於合法性的高速DDoS封包過濾在Intel IXP1200上的案例研究和實現，Roshan K. Thomas、Brian Mark、Tommy Johnson和James Croall
第13章 網絡處理器的封包分類方向，Michael E. Kounavis、Alok Kumar、Harrick Vin、Raj Yavatkar和Andrew T. Campbell
第二部分 實踐
第14章 使用Agere網絡處理器解決方案實現高性能、高價值的流量管理，Jian-Guo Chen、David Sonnier、Robert Munoz、Vinoj Kumar和Ambalavanar Arulambalam
第15章 AMCC - nPcoreTM “NISC”架構，Robin Melnick和Keith Morris
第16章 網絡處理器中的適應性帶寬分配以支持QoS，Clark Jeffries、Mohammad Peyravian和Ravi Sabhikhi