ASIC and FPGA Verification : A Guide to Component Modeling

Richard Munden

  • 出版商: Morgan Kaufmann
  • 出版日期: 2004-10-13
  • 售價: $2,445
  • 貴賓價: 9.5$2,323
  • 語言: 英文
  • 頁數: 336
  • 裝訂: Hardcover
  • ISBN: 0125105819
  • ISBN-13: 9780125105811

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Description:

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

 

Table of Contents:

1.Introduction to Board-Level Verification; 2.Tour of a simple model; 3.VHDL packages for component models; 4.Introduction to SDF; 5.Anatomy of a VITAL Model; 6.Modeling Delays; 7.VITAL truth tables; 8.Modeling timing constraints; 9.Modeling registered devices; 10.Conditional delays and timing constraints; 11.Negative timing constraints; 12.Timing Files and Backannotation; 13.Adding Timing to Your RTL Code; 14.Modeling Memories; 15.Considerations for Component Modeling; 16.Modeling Component Centric Features; 17.Testbenches for Component Models