Power Integrity for I/O Interfaces: With Signal Integrity/ Power Integrity Co-Design (美國原版)

Foreword by Joungho Kim

The Hands-On Guide to Power Integrity in Advanced Applications, from Three Industry Experts

In this book, three industry experts introduce state-of-the-art power integrity design techniques for today’s most advanced digital systems, with real-life, system-level examples. They introduce a powerful approach to unifying power and signal integrity design that can identify signal impediments earlier, reducing cost and improving reliability.

After introducing high-speed, single-ended and differential I/O interfaces, the authors describe on-chip, package, and PCB power distribution networks (PDNs) and signal networks, carefully reviewing their interactions. Next, they walk through end-to-end PDN and signal network design in frequency domain, addressing crucial parameters such as self and transfer impedance. They thoroughly address modeling and characterization of on-chip components of PDNs and signal networks, evaluation of power-to-signal coupling coefficients, analysis of Simultaneous Switching Output (SSO) noise, and many other topics.

Coverage includes

• The exponentially growing challenge of I/O power integrity in high-speed digital systems

• PDN noise analysis and its timing impact for single-ended and differential interfaces

• Concurrent design and co-simulation techniques for evaluating all power integrity effects on signal integrity

• Time domain gauges for designing and optimizing components and systems

• Power/signal integrity interaction mechanisms, including power noise coupling onto signal trace and noise amplification through signal resonance

• Performance impact due to Inter Symbol Interference (ISI), crosstalk, and SSO noise, as well as their interactions

• Validation techniques, including low impedance VNA measurements, power noise measurements, and characterization of power-to-signal coupling effects

Power Integrity for I/O Interfaces will be an indispensable resource for everyone concerned with power integrity in cutting-edge digital designs, including system design and hardware engineers, signal and power integrity engineers, graduate students, and researchers.

「高級應用中的電源完整性實踐指南」序言，金鍾鎬撰寫

這本書由三位業界專家介紹了當今最先進的數字系統的電源完整性設計技術，並提供了實際的系統級例子。他們介紹了一種強大的方法，可以統一電源和信號完整性設計，並能夠更早地識別信號阻礙，從而降低成本並提高可靠性。

在介紹高速單端和差分I/O接口之後，作者們詳細描述了芯片、封裝和PCB的電源分配網絡（PDN）和信號網絡，並仔細審查它們之間的相互作用。接下來，他們通過頻域進行端到端的PDN和信號網絡設計，並解決了自身和傳輸阻抗等關鍵參數。他們全面介紹了PDN和信號網絡的芯片內部組件建模和表徵、功率到信號耦合係數評估、同時切換輸出（SSO）噪聲分析等多個主題。

內容包括：

• 高速數字系統中I/O電源完整性的指數級增長挑戰

• 單端和差分接口的PDN噪聲分析及其對時序的影響

• 同時設計和協同模擬技術，用於評估所有電源完整性對信號完整性的影響

• 設計和優化元件和系統的時域評估方法

• 電源噪聲對信號追蹤的耦合和信號共振引起的噪聲放大等電源/信號完整性相互作用機制

• 由間符號干擾（ISI）、串擾和SSO噪聲引起的性能影響，以及它們之間的相互作用

• 驗證技術，包括低阻抗VNA測量、電源噪聲測量和功率到信號耦合效應的表徵

「I/O接口的電源完整性」將成為所有關心尖端數字設計中電源完整性的人的不可或缺的資源，包括系統設計和硬件工程師、信號和電源完整性工程師、研究生和研究人員。