Power Integrity for I/O Interfaces: With Signal Integrity/ Power Integrity Co-Design (美國原版)
暫譯: I/O 介面的電源完整性:信號完整性/電源完整性共同設計
Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi
- 出版商: Prentice Hall
- 出版日期: 2010-10-15
- 售價: $4,500
- 貴賓價: 9.8 折 $4,410
- 語言: 英文
- 頁數: 416
- 裝訂: Hardcover
- ISBN: 0137011199
- ISBN-13: 9780137011193
-
相關分類:
電路學 Electric-circuits
立即出貨
買這商品的人也買了...
-
High Speed Digital Design: A Handbook of Black Magic (Hardcover)$5,150$4,893 -
High-Speed Signal Propagation : Advanced Black Magic (美國原版)$4,680$4,586 -
深入淺出 Java 程式設計, 2/e (Head First Java, 2/e)$880$695 -
Jitter, Noise, and Signal Integrity at High-Speed (Hardcover)$4,110$3,905 -
Power Integrity Modeling and Design for Semiconductors and Systems (Hardcover)$4,430$4,209 -
Digital Communications Test and Measurement: High-Speed Physical Layer Characterization (美國原版)$4,300$4,214 -
大話設計模式$620$490 -
iPhone 創意程式設計家, 2/e (適用 SDK 3、SDK 4)$530$419 -
全球最強 VMware vSphere 4 企業環境建構$860$731 -
鳥哥的 Linux 私房菜-基礎學習篇, 3/e$820$648 -
Power Integrity Analysis and Management for Integrated Circuits (Hardcover)$4,430$4,209 -
Visual C# 2010 程式設計經典$650$514 -
演算法之道─讓你學不會演算法都難$420$332 -
$3,150Signal and Power Integrity - Simplified, 2/e (Hardcover) -
前進 Android Market!Google Android SDK 實戰演練$850$672 -
Google Android SDK 開發範例大全, 3/e$950$751 -
高科技廠務, 3/e$480$432 -
Small Antenna Handbook (Hardcover)$1,580$1,548 -
通訊專業英語$520$468 -
$408Cadence高速電路板設計與模擬--信號與電源完整性分析(第4版) -
$276Cadence系統級封裝設計--Allegro SiP\APD設計指南 -
電磁相容分析與設計 : 從 PI 與 SI 根因探討$720$706 -
Signal and Power Integrity - Simplified, 3/e (Hardcover)$4,800$4,704 -
信號完整性與電源完整性分析, 3/e (Signal and Power Integrity - Simplified, 3/e)$774$735 -
PDN 設計之電源完整性:高速數字產品的魯棒和高效設計 (Principles of Power Integrity for PDN Design--Simplified: Robust and Cost Effective Design for High Speed Digital Products)$1,194$1,134
相關主題
商品描述
Foreword by Joungho Kim
The Hands-On Guide to Power Integrity in Advanced Applications, from Three Industry Experts
In this book, three industry experts introduce state-of-the-art power integrity design techniques for today’s most advanced digital systems, with real-life, system-level examples. They introduce a powerful approach to unifying power and signal integrity design that can identify signal impediments earlier, reducing cost and improving reliability.
After introducing high-speed, single-ended and differential I/O interfaces, the authors describe on-chip, package, and PCB power distribution networks (PDNs) and signal networks, carefully reviewing their interactions. Next, they walk through end-to-end PDN and signal network design in frequency domain, addressing crucial parameters such as self and transfer impedance. They thoroughly address modeling and characterization of on-chip components of PDNs and signal networks, evaluation of power-to-signal coupling coefficients, analysis of Simultaneous Switching Output (SSO) noise, and many other topics.
Coverage includes
• The exponentially growing challenge of I/O power integrity in high-speed digital systems
• PDN noise analysis and its timing impact for single-ended and differential interfaces
• Concurrent design and co-simulation techniques for evaluating all power integrity effects on signal integrity
• Time domain gauges for designing and optimizing components and systems
• Power/signal integrity interaction mechanisms, including power noise coupling onto signal trace and noise amplification through signal resonance
• Performance impact due to Inter Symbol Interference (ISI), crosstalk, and SSO noise, as well as their interactions
• Validation techniques, including low impedance VNA measurements, power noise measurements, and characterization of power-to-signal coupling effects
Power Integrity for I/O Interfaces will be an indispensable resource for everyone concerned with power integrity in cutting-edge digital designs, including system design and hardware engineers, signal and power integrity engineers, graduate students, and researchers.
商品描述(中文翻譯)
前言 由金鍾浩撰寫
來自三位業界專家的高級應用電源完整性實用指南
在本書中,三位業界專家介紹了當今最先進數位系統的尖端電源完整性設計技術,並提供了實際的系統級範例。他們提出了一種強大的方法來統一電源和信號完整性設計,能夠更早識別信號阻抗,從而降低成本並提高可靠性。
在介紹高速、單端和差分 I/O 接口後,作者描述了晶片內、封裝和 PCB 的電源分配網路 (PDNs) 和信號網路,仔細回顧它們之間的互動。接下來,他們將在頻域中逐步講解端到端的 PDN 和信號網路設計,處理自我和轉移阻抗等關鍵參數。他們徹底探討了 PDNs 和信號網路的晶片內元件建模和特性化、電源與信號耦合係數的評估、同時切換輸出 (SSO) 噪聲的分析,以及許多其他主題。
內容涵蓋
• 在高速數位系統中,I/O 電源完整性日益增長的挑戰
• PDN 噪聲分析及其對單端和差分接口的時序影響
• 同時設計和共同模擬技術,用於評估所有電源完整性對信號完整性的影響
• 設計和優化元件及系統的時間域測量工具
• 電源/信號完整性互動機制,包括電源噪聲耦合到信號線路和通過信號共振的噪聲放大
• 由於符號間干擾 (ISI)、串擾和 SSO 噪聲及其互動所造成的性能影響
• 驗證技術,包括低阻抗 VNA 測量、電源噪聲測量和電源與信號耦合效應的特性化
I/O 接口的電源完整性 將成為所有關心尖端數位設計中電源完整性的人士不可或缺的資源,包括系統設計和硬體工程師、信號和電源完整性工程師、研究生和研究人員。
