A Practical Guide for SystemVerilog Assertions (Hardcover)

Srikanth Vijayaraghavan, Meyyappan Ramanathan

  • 出版商: Springer
  • 出版日期: 2005-06-01
  • 售價: $7,550
  • 貴賓價: 9.5$7,173
  • 語言: 英文
  • 頁數: 334
  • 裝訂: Hardcover
  • ISBN: 0387260498
  • ISBN-13: 9780387260495
  • 相關分類: Verilog

下單後立即進貨 (約1週~2週)

買這商品的人也買了...

相關主題

商品描述

SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench.  Assertions add a whole new dimension to the ASIC verification process.   Engineers are used to writing testbenches in verilog that help verify their design.  Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today.  SystemVerilog assertions (SVA) is a declarative language.  The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously.  This provides the engineers a very strong tool to solve their verification problems.  The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language.  There is not enough expertise or intellectual property available as of today in the field.  While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.  This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.