Logic Synthesis and Verification Algorithms

Gary D. Hachtel, Fabio Somenzi

  • 出版商: Springer
  • 出版日期: 2006-02-10
  • 售價: $3,660
  • 貴賓價: 9.5$3,477
  • 語言: 英文
  • 頁數: 564
  • 裝訂: Paperback
  • ISBN: 0387310045
  • ISBN-13: 9780387310046
  • 相關分類: 資料結構與演算法

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Description

This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

 

Table of Contents

I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.