Logic Synthesis and Verification Algorithms

Gary D. Hachtel, Fabio Somenzi

  • 出版商: Springer
  • 出版日期: 2006-02-10
  • 售價: $3,740
  • 貴賓價: 9.5$3,553
  • 語言: 英文
  • 頁數: 564
  • 裝訂: Paperback
  • ISBN: 0387310045
  • ISBN-13: 9780387310046
  • 相關分類: Algorithms-data-structures
  • 無法訂購

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商品描述

Description

This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

 

Table of Contents

I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.

商品描述(中文翻譯)

描述

本書將數學基礎和算法發展與電路設計問題相結合。每種新技術都是在其應用於設計的背景下介紹的。通過研究最佳的二級和多級組合電路設計,讀者將被介紹到基本概念,如布爾代數、局部搜索和代數分解。同樣,通過研究最佳的時序電路設計,讀者將被介紹到圖算法、有限狀態系統和語言理論。在整本書中,使用了分支界限、動態規劃和符號隱式枚舉等重複出現的主題來建立最佳設計原則。

目錄

I:引言。1. 引言。2. 通過一個簡單的例子快速了解邏輯合成。

II:二級邏輯合成。3. 布爾代數。4. 二級電路的合成。5. 二級電路的啟發式最小化。6. 二進制決策圖(BDD)。

III:時序系統模型。7. 時序系統模型。8. 有限狀態機的合成和驗證。9. 有限自動機。

IV:多級邏輯合成。10. 多級邏輯合成。11. 多級最小化。12. 組合電路的自動測試生成。13. 技術映射。A. ASCII 碼。B. 附加問題。

參考文獻。

索引。