ESD : RF Technology and Circuits (Hardcover)

Steven H. Voldman

  • 出版商: Wiley
  • 出版日期: 2006-10-06
  • 售價: $2,080
  • 貴賓價: 9.8$2,038
  • 語言: 英文
  • 頁數: 420
  • 裝訂: Hardcover
  • ISBN: 0470847557
  • ISBN-13: 9780470847558

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Electrostatic Discharge (ESD) within RF devices can result in the malfunctioning of nearby electronic equipment. This volume is designed as the third in a series of three books addressing Electrostatic Discharge (ESD) physics, devices, circuits and design. It will be the first book to address the increasingly important area of ESD within RF devices and circuits.


Table of Contents



Chapter 1. RF DESIGN and ESD.

1.1 Fundamental Concepts of ESD design.

1.2 Fundamental Concepts of RF ESD Design.

1.3 Key RF ESD Contributions.

1.4 Key RF ESD Patents.

1.5 ESD Failure Mechanisms.

1.5.1 RF CMOS ESD Failure Mechanisms.

1.5.2 Silicon Germanium ESD Failure Mechanisms.

1.5.3 Silicon Germanium Carbon ESD Failure Mechanisms.

in Silicon Germanium Carbon Devices.

1.5.4 Gallium Arsenide Technology ESD Failure Mechanisms.

1.5.5 Indium Gallium Arsenide ESD Failure Mechanisms.

1.5.6. RF Bipolar Circuits ESD Failure Mechanisms.

1.6 RF Basics.

1.7 Two-Port Network Parameters.

1.7.1 Z - Parameters.

1.7.2 Y – Parameters.

1.7.3. S – Parameters.

1.7.4 T - Parameters.

1.8. Stability: RF Design Stability and ESD.

1.9 Device Degradation and ESD Failure.

1.9.1. ESD-induced D.C. Parameter Shift and Failure Criteria.

1.9.2 RF Parameters, ESD Degradation, and Failure Criteria.

1.10 RF ESD Testing.

1.10.1 ESD Testing Models.

1.10.2 RF Maximum Power-to-Failure and ESD Pulse.

Testing Methodology.

1.10.3 ESD-Induced RF Degradation and S- Parameter.

Evaluation Test Methodology.

1.11 Time Domain Reflection (TDR) and Impedance Methodology.

for ESD Testing.

1.11.1 Time Domain Reflectometry (TDR) ESD Test System Evaluation.

1.11.2 ESD Degradation System Level Method – Eye Tests.

1.12 Product Level ESD Test and RF Functional Parameter Failure.

1.13 Combined RF and ESD TLP Test Systems.

1.14 Closing Comments and Summary.



Chapter 2. RF ESD Design.

2.1 ESD Design Methods: Ideal ESD networks and RF.

ESD Design Windows.

2.1.1 Ideal ESD Networks and the Current–Voltage.

d.c. Design Window.

2.1.2 Ideal ESD Networks in the Frequency Domain Design Window.

2.2 RF ESD Design Methods: Linearity.

2.3 RF ESD Design: Passive Element Quality Factors and Figures of Merit.

2.4 RF ESD Design Methods: Method of Subsitution.

2.4.1 Method of Substitution of Passive element to ESD.

Network Element.

2.4.2 Substitution of ESD Network Element to Passive Element.

2.5 RF ESD Design Methods: Matching Networks and RF ESD Networks.

2.5.1 RF ESD Methods–Conversion of Matching.

Networks to ESD Networks.

2.5.3 RF ESD Method: Conversion of ESD Networks into.

Matching Networks. Conversion of ESD Networks into L-Match Networks. Conversion of ESD Networks into II-Match Networks. Conversion of ESD Networks into T-Match Networks.

2.6 RF ESD Design Methods: Inductive Shunt.

2.7 RF ESD Design Methods: Cancellation Method.

2.7.1 Quality Factors and the Cancellation Method.

2.7.2 Inductive Cancellation of Capacitance Load and.

Figures of Merit.

2.7.3 Cancellation Method and ESD Circuitry.

2.8 RF ESD Design Methods: Impedance Isolation Technique Using.

LC Resonator.

2.9 RF ESD Design Methods: Lumped versus Distributed Loads.

2.9.1 RF ESD Distributed Load with Coplanar Wave Guides.

2.9.2 RF ESD Distribution Coplanar Waveguides Analysis.

Using ABCD Matrices.

2.10 ESD RF Design Synthesis and Floor Planning: RF, Analog, and.

Digital Integration.

2.10.1 ESD Power Clamp Placement Within a Domain.

2.10.2 Power Bus Architecture and ESD Design Synthesis.

2.10.3 VDD-to-VSS Power Rail Protection.

2.10.4 VDD-to-Analog VDD and VDD-to-RF VCC Power Rail Protection.

2.10.5 Interdomain ESD protection networks.

2.11 ESD Circuits and RF Bond Pad Integration.

2.12 ESD Structures Under Wire Bond Pads.

2.13 Summary and Closing Comments.



Chapter 3. RF CMOS and ESD.

3.1 RF CMOS: ESD Device Comparisons.

3.2 Circular RF ESD Devices.

3.3 RF ESD Design—ESD Wiring Design.

3.4 RF Passives: ESD and Schottky Barrier Diodes.

3.5 RF Passives: ESD and Inductors.

3.6 RF Passives: ESD and Capacitors.

3.6.1 Metal-oxide-Semiconductor and Metal–Insulator–Metal.


3.6.2 Varactors and Hyper-Abrupt Junction Varactor Capacitors.

3.6.3 Metal-ILD-Metal Capacitors.

3.6.4 Vertical Parallel Plate (VPP) Capacitors.

3.7 Summary and Closing Comments.



Chapter 4. RF CMOS ESD Networks.

4.1 RF CMOS Input Circuits.

4.1.1 RF CMOS ESD Diode Networks.

4.1.2 RF CMOS Diode String ESD Network.

4.2 RF CMOS: Diode–Inductor ESD Networks.

4.2.1 RF Inductor–Diode ESD Networks.

4.2.2 RF Diode–Inductor ESD Networks.

4.3 RF CMOS Impedance Isolation LC Resonator ESD Networks.

4.3.1 RF CMOS LC–Diode ESD Networks.

4.3.2 RF CMOS Diode–LC ESD Networks.

4.3.3 Experimental Results of the RF CMOS LC–Diode Networks.

4.4 RF CMOS LNA ESD Design.

4.4.1 RF LNA ESD Design: Low Resistance ESD Inductor and.

ESD Diode Clamping Elements in II-Configuration.

4.5 RF CMOS T-Coil Inductor ESD Input Network.

4.6 RF CMOS Distributed ESD Networks.

4.6.1 RF CMOS Distributed RF ESD Networks.

4.6.2 RF CMOS Distributed RF ESD Networks using Series.

Inductor and Dual-Diode Shunt.

4.6.3 RF CMOS Distributed RF ESD Networks using Series.

Inductor and MOSFET Parallel Shunt.

4.7 RF CMOS Distributed ESD Networks: Transmission Lines.

and Co-planar Waveguides.

4.8 RF CMOS: ESD and RF LDMOS Power Technology.

4.9 RF CMOS ESD Power Clamps.

4.9.1 RC-Triggered MOSFET ESD Power Clamp.

4.9.2 High Voltage RC-Triggered MOSFET ESD Power Clamp.

4.9.3 Voltage-Triggered MOSFET ESD Power Clamps.

4.10 Summary and Closing Comments.



Chapter 5. Bipolar Physics.

5.1 Bipolar Device Physics.

5.1.1 Bipolar Transistor Current Equations.

5.1.2 Bipolar Current Gain and Collector-to-Emitter Transport.

5.1.3 Unity Current Gain Cutoff Frequency.

5.1.4 Unity Power Gain Cutoff Frequency.

5.2 Transistor Breakdown.

5.2.1 Avalanche Multiplication and Breakdown.

5.2.2 Bipolar Transistor Breakdown.

5.3 Kirk Effect.

5.4 Johnson Limit: Physical Limitations of the Transistor.

5.4.1 Voltage–Frequency Relationship.

5.4.2 Johnson Limit Current–Frequency Formulation.

5.4.3 Johnson Limit Power Formulation.

5.5 RF Instability: Emitter Collapse.

5.6 ESD RF Design Layout: Emitter, Base, and Collector Configurations.

5.7 ESD RF Design Layout: Utilization of a Second.

Emitter (Phantom Emitter).

5.8 ESD RF Design Layout: Emitter Ballasting.

5.9 ESD RF Design Layout: Thermal Shunts and Thermal Lenses.

5.10 Base-Ballasting and RF Stability.

5.11 Summary and Closing Comments.



Chapter 6. Silicon Germanium and ESD.

6.1 Heterojunctions and Silicon Germanium Technology.

6.1.1 Silicon Germanium HBT Devices.

6.1.2 Silicon Germanium Device Structure.

6.2 Silicon Germanium Physics.

6.3 Silicon Germanium Carbon.

6.4 Silicon Germanium ESD Measurements.

6.4.1 Silicon Germanium Collector-to-Emitter ESD Stress.

6.4.2 ESD Comparison of Silicon Germanium HBT and Silicon BJT.

6.4.3 SiGe HBT Electrothermal Human Body Model (HBM) Simulation of.

Collector–Emitter Stress.

6.5. Silicon Germanium Carbon Collector–Emitter ESD Measurements.

6.6 Silicon Germanium Transistor Emitter–Base Design.

6.6.1 Epitaxial–Base Heterojunction Bipolar Transistor (HBT).

Emitter-Base Design.

6.6.2 Emitter–Base Design RF Frequency Performance Metrics.

6.6.3 SiGe HBT Emitter–Base Resistance Model.

6.6.4 SiGe HBT Emitter–Base Design and Silicide Placement.

6.6.5 Self-Aligned (SA) Emitter–Base Design.

6.6.6 Non-self aligned (NSA) Emitter–Base Design. NSA Human Body Model (HBM) Step Stress. Transmission Line Pulse (TLP) Step Stress. RF Testing of SiGe HBT Emitter–Base Configuration. Unity Current Gain Cutoff Frequency–Collector.

Current Plots.

6.6.7 Silicon Germanium Carbon–ESD-Induced S- Parameter.


6.6.8 Electrothermal Simulation of Emitter–Base Stress.

6.7 Field-Oxide (FOX) Isolation Defined Silicon Germanium.

Heterojunction Bipolar Transistor HBM data.

6.8 Silicon Germanium HBT Multiple-Emitter Study.

6.9 Summary and Closing Comments.



Chapter 7. Gallium Arsenide and ESD.

7.1 Gallium Arsenide Technology and ESD.

7.2 Gallium Arsenide Energy-to-Failure and Power-to-Failure.

7.3 Gallium Arsenide ESD Failures in Active and Passive Elements.

7.4 Gallium Arsenide HBT Devices and ESD.

7.4.1 Gallium Arsenide HBT Device ESD Results.

7.4.2 Gallium Arsenide HBT Diode Strings.

7.5 Gallium Arsenide HBT-Based Passive Elements.

7.5.1 GaAs HBT Base–Collector Varactor.

7.6 Gallium Arsenide Technology Table of Failure Mechanisms.

7.7 Indium Gallium Arsenide and ESD.

7.8 Indium Phosphide (InP) and ESD.

7.9 Summary and Closing Comments.



Chapter 8. Bipolar Receiver Circuits and Bipolar ESD Networks.

8.1 Bipolar Receivers and ESD.

8.2 Single Ended Common-Emitter Receiver Circuits.

8.2.1 Single-Ended Bipolar Receiver with D.C. Blocking Capacitors.

8.2.2 Bipolar Receiver with D.C. Blocking Capacitors.

and ESD Protection.

8.2.3 Receivers Bipolar Single-Ended Common Emitter with.

Feedback Circuit. Receivers Bipolar Single-Ended Common-Emitter.

Circuit with Resistor Feedback Element. Receivers Single-Ended Common-Emitter Receiver.

Circuit with Resistor-Capacitor Feedback Element.

8.2.4 Receivers Bipolar Single-Ended Common Emitter with.

Emitter Degeneration Element.

8.2.5 Bipolar Single-Ended Common Emitter Circuit with.

Balun Output.

8.2.6 Bipolar Single-Ended Series Cascode Receiver Circuits.

8.3 Bipolar Differential Receiver Circuits.

8.3.1. Bipolar Differential Cascode Common-Emitter.

Receiver Circuits.

8.4 Bipolar ESD Input Circuits.

8.4.1 Diode-Configured Bipolar ESD Input Circuits.

8.4.2 Bipolar ESD Input: Resistor Grounded Base.

Bipolar ESD Input.

8.5 Bipolar-based ESD Power Clamps.

8.5.1 Bipolar Voltage-Triggered ESD Power Clamps.

8.5.2 Zener Breakdown Voltage-Triggered ESD Power Clamp.

8.5.3 BVCEO Voltage Triggered ESD Power Clamp.

8.5.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO-.

Breakdown Synthesized Bipolar ESD Power Clamps.

8.5.5 Ultra-Low Voltage Forward-Biased Voltage-Trigger.

BiCMOS ESD Power Clamp.

8.5.6 Capacitively-Triggered BiCMOS ESD Power Clamp.

8.6 Bipolar ESD Diode String and Triple-Well Power Clamps.

8.7 Summary and Closing Comments.



Chapter 9. RF and ESD Computer-Aided Design (CAD).

9.1 RF ESD Design Environment.

9.1.1 Electrostatic Discharge and Radio Frequency (RF).

Cosynthesis Design Method.

9.1.2 ESD Hierarchical Pcell Physical Layout Generation.

9.1.3 ESD Hierarchical Pcell Schematic Generation.

9.2 ESD Design with Hierarchical Parameterized Cells.

9.2.1 Hierarchical Pcell Graphical Method.

9.2.2 Hiearchical Pcell Schematic Method.

9.3 ESD Design of RF CMOS-Based Hierarchical Parameterized Cells.

9.4 RF BiCMOS ESD Hierarchical Parameterized Cell.

9.4.1 BiCMOS ESD Input Networks.

9.4.2 BiCMOS ESD Rail-to-Rail.

9.4.3 BiCMOS ESD Power Clamp.

9.5 Advantages and Limitations of the ESD Design System.

9.6 Guard Ring P-Cell Methodology.

9.6.1 Guard Rings for Internal and External Latchup Phenomena.

9.6.2 Guard Ring Theory.

9.6.3 Guard Ring Design.

9.6.4 Guard Ring Characterization.

9.7 Summary and Closing Comments.



Chapter 10. Alternative ESD Concepts: On-Chip and Off-Chip.

ESD Protection Solutions.

10.1 Spark Gaps.

10.2 Field Emission Devices.

10.2.1 Field Emission Device (FED) as ESD Protection.

10.2.2 Field Emission Device in Gallium Arsenide Technology.

10.2.3 Field Emission Device Electronic Blunting Effect.

10.2.4 Field Emission Device Multiemitter ESD Design.

10.2.5 Field Emission Device (FED) ESD Design Practices.

10.3 Off-chip Protection and Off-Chip Transient Suppression Devices.

10.4 Off-Chip Transient Voltage Suppression (TVS) Devices.

10.5 Off-Chip Polymer Voltage Suppression (PVS) Devices.

10.6 Package-Level Mechanical ESD Solutions.

10.7 RF Proximity Communications Chip-to-Chip ESD Design Practices.

10.8 Summary and Closing Comments.