Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL (Hardcover)

Mohammed Ferdjallah

  • 出版商: Wiley
  • 出版日期: 2011-07-05
  • 售價: $3,880
  • 貴賓價: 9.5$3,686
  • 語言: 英文
  • 頁數: 232
  • 裝訂: Hardcover
  • ISBN: 0470900555
  • ISBN-13: 9780470900550
  • 下單後立即進貨 (約1~3週)


Digital systems design requires a rigorous modeling and simulation analysis that eliminates design risks and potential harm to users. Introduction to Digital Systems Modeling and Simulation allows readers to model and simulate digital principles using Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming. Extensively classroom and laboratory tested, the text provides scholars, practitioners, and students with learning objectives at the beginning of each chapter as well as the practical application of modeling and synthesis to digital system design to establish a basis for effective design.