Introduction to Advanced System-on-Chip Test Design and Optimization (Hardvover)

Erik Larsson

  • 出版商: Springer
  • 出版日期: 2005-11-07
  • 售價: $1,200
  • 貴賓價: 9.8$1,176
  • 語言: 英文
  • 頁數: 388
  • 裝訂: Hardcover
  • ISBN: 1402032072
  • ISBN-13: 9781402032073
  • 下單後立即進貨 (約5~7天)

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商品描述

Description

Testing of Integrated Circuits is important to ensure the production of fault-free chips. However, testing is becoming cumbersome and expensive due to the increasing complexity of these ICs. Technology development has made it possible to produce chips where a complete system, with an enormous transistor count, operating at a high clock frequency, is placed on a single die - SOC (System-on-Chip). The device size miniaturization leads to new fault types, the increasing clock frequencies enforces testing for timing faults, and the increasing transistor count results in a higher number of possible fault sites. Testing must handle all these new challenges in an efficient manner having a global system perspective.

 

Test design is applied to make a system testable. In a modular core-based environment where blocks of reusable logic, the so called cores, are integrated to a system, test design for each core include: test method selection, test data (stimuli and responses) generation (ATPG), definition of test data storage and partitioning [off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST (Built-In Self-Test)], wrapper selection and design (IEEE std 1500), TAM (test access mechanism) design, and test scheduling minimizing a cost function whilst considering limitations and constraint. A system test design perspective that takes all the issues above into account is required in order to develop a globally optimized solution.

 

SOC test design and its optimization is the topic of this book. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process.

 

Table of contents

Part I. Testing Concepts. Introduction. Design Flow. Design for Test. Boundary Scan.- Part II. SoC Design for Testability. System Modeling. Test Conflicts. Test Power Dissipation. Test Access Mechanism. Test Scheduling.- Part III. SoC Test Applications. A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling. An Integrated Framework for the Design and Optimization of SoC Test Solutions. Efficient Test Solutions for Core-Based Designs. Integrating Core Selection in the System-On-Chip Test Solution Design-Flow. Defect-Aware Test Scheduling. An Integrated Technique for Test Vector Selection and Test Scheduling Under Ate Memory Depth Constraint.- Appendix 1. Benchmarks.- References.- Index.

商品描述(中文翻譯)

描述

集成電路測試對於確保生產無故障晶片至關重要。然而,由於這些集成電路的複雜性不斷增加,測試變得繁瑣且昂貴。技術的發展使得能夠在單一晶片上放置一個具有龐大晶體管數量且以高時鐘頻率運行的完整系統 - SOC(片上系統)。設備尺寸的微型化導致了新的故障類型,不斷增加的時鐘頻率強制進行時序故障測試,而不斷增加的晶體管數量則導致可能的故障點數量增加。測試必須以全球系統視角高效處理所有這些新挑戰。

測試設計用於使系統可測試。在模塊化核心為基礎的環境中,將可重用邏輯塊(稱為核心)集成到系統中,每個核心的測試設計包括:測試方法選擇,測試數據(刺激和響應)生成(ATPG),測試數據存儲和分區定義(作為ATE(自動測試設備)的外部芯片和/或作為BIST(內建自測)的內部芯片),封裝選擇和設計(IEEE std 1500),測試訪問機制(TAM)設計,以及測試調度,同時考慮限制和約束,最小化成本函數。需要一個全球優化的解決方案來考慮所有上述問題的系統測試設計視角。

本書的主題是SOC測試設計及其優化。它介紹了測試,描述了與SOC測試相關的問題,討論了建模粒度以及在EDA(電子設計自動化)工具中的實現。本書分為三個部分:i)測試概念,ii)用於測試的SOC設計,以及iii)SOC測試應用。第一部分涵蓋了測試問題的介紹,包括故障,故障類型,設計流程,設計測試技術,如掃描測試和邊界掃描。本書的第二部分討論了與SOC相關的問題,如系統建模,測試衝突,功耗,測試訪問機制設計,測試調度和缺陷導向調度。最後,第三部分專注於SOC應用,例如集成測試調度和TAM設計,缺陷導向調度,以及將測試設計與核心選擇過程集成。

目錄

第一部分。測試概念。介紹。設計流程。測試設計。邊界掃描。
第二部分。SOC測試性設計。系統建模。測試衝突。測試功耗。測試訪問機制。測試調度。
第三部分。SOC測試應用。可重構的節能核心封裝及其在SOC測試調度中的應用。用於SOC測試解決方案設計和優化的集成框架。基於核心的設計的高效測試解決方案。將核心選擇集成到SOC測試解決方案設計流程中。缺陷感知測試調度。在ATE記憶深度約束下的測試向量選擇和測試調度的集成技術。
附錄1。基準。
參考文獻。
索引。