Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design (Hardocver)
David Chinnery, Kurt Keutzer
- 出版商: Springer
- 出版日期: 2002-06-30
- 售價: $6,980
- 貴賓價: 9.5 折 $6,631
- 語言: 英文
- 頁數: 414
- 裝訂: Hardcover
- ISBN: 1402071132
- ISBN-13: 9781402071133
This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times.
Important topics include:
- Improving performance through microarchitecture;
- Timing-driven floorplanning;
- Controlling and exploiting clock skew;
- High performance latch-based design in an ASIC methodology;
- Automatically identifying and synthesizing complex logic gates;
- Automated cell sizing to increase performance and reduce power;
- Controlling process variation.
These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.
Table of Contents
Preface. List of trademarks. 1. Introduction and Overview of the Book; D. Chinnery, K. Keutzer.
2. Improving Performance through Microarchitecture; D. Chinnery, K. Keutzer. 3. Reducing the Timing Overhead; D. Chinnery, K. Keutzer. 4. High-Speed Logic, Circuits, Libraries and Layout; A. Chang, et al. 5. Finding Peak Performance in a Process; D. Chinnery, K. Keutzer.
6. Physical Prototyping Plans for High Performance; M. Courtoy, et al. 7. Automatic Replacement of Flip-Flops by Latches in ASIC's; D. Chinnery, et al. 8. Useful-Skew Clock Synthesis Boosts ASIC Performance; W. Dai, D. Staepelaere. 9. Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing; M. Côté, P. Hurat. 10. Design Optimization with Automated Flex-Cell Creation; D. Bhattacharya, V. Boppana. 11. Exploiting Structure and Managing Wires to Increase Density and Performance; A. Chang, W.J. Dally. 12. Semi-Custom Methods in a High-Performance Microprocessor Design; G.A. Northrop. 13. Controlling Uncertainty in High Frequency Designs; S.E. Rich, et al. 14. Increasing Circuit Performance through Statistical Design Techniques; M. Orshansky.
15. Achieving 550MHz in a Standard Cell ASIC Methodology; D. Chinnery, et al. 16. The iCORE® 520MHz Synthesizable CPU Core; N. Richardson, et al. 17. Creating Synthesizable ARM Processors with Near Custom Performance; D. Flynn, M. Keating.