Nano-CMOS Gate Dielectric Engineering (Hardcover)

According to Moore’s Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT.

This comprehensive, up-to-date text covering the physics, materials, devices, and fabrication processes for high-k gate dielectric materials, Nano-CMOS Gate Dielectric Engineering systematically describes how the fundamental electronic structures and other material properties of the transition metals and rare earth metals affect the electrical properties of the dielectric films, the dielectric/silicon and the dielectric/metal gate interfaces, and the resulting device properties. Specific topics include the problems and solutions encountered with high-k material thermal stability, defect density, and poor initial interface with silicon substrate. The text also addresses the essence of thin film deposition, etching, and process integration of high-k materials in an actual CMOS process.

Fascinating in both content and approach, Nano-CMOS Gate Dielectric Engineering explains all of the necessary physics in a highly readable manner and supplements this with numerous intuitive illustrations and tables. Covering almost every aspect of high-k gate dielectric engineering for nano-CMOS technology, this is a perfect reference book for graduate students needing a better understanding of developing technology as well as researchers and engineers needing to get ahead in microelectronic engineering and materials science.

根據摩爾定律，集成電路中的晶體管數量不僅每兩年翻倍，晶體管的尺寸也以可預測的速率減小。按照目前的速度，CMOS晶體管的尺寸將在2020年達到十納米的規模。因此，為了保持晶體管的正常運作，閘極介電層的厚度將被縮小到不到半納米的氧化物等效厚度（EOT），這樣小尺寸的EOT只有高介電材料才是可行的解決方案。

這本全面且最新的書籍《納米CMOS閘極介電層工程》涵蓋了高介電閘極介電層材料的物理、材料、器件和製造工藝，系統地描述了過渡金屬和稀土金屬的基本電子結構和其他材料性質如何影響介電薄膜、介電質/矽和介電質/金屬閘極界面的電性以及相應的器件性能。具體主題包括高介電材料熱穩定性、缺陷密度和與矽基板的初始界面問題以及相關解決方案。該書還討論了高介電材料在實際CMOS工藝中的薄膜沉積、蝕刻和工藝整合的要點。

《納米CMOS閘極介電層工程》的內容和方法都非常引人入勝，以易讀的方式解釋了所有必要的物理知識，並配有眾多直觀的插圖和表格。涵蓋了幾乎所有納米CMOS技術中高介電閘極介電層工程的方方面面，這是研究生需要更好地理解發展中技術的完美參考書，也是研究人員和工程師在微電子工程和材料科學領域取得領先地位的必備工具。