商品描述
The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines.
商品描述(中文翻譯)
Verilog 硬體描述語言(Verilog-HDL)長期以來一直是描述複雜數位硬體的最受歡迎語言。它最初是一種專有語言,但由 Cadence Design Systems 捐贈給設計社群,以作為開放標準的基礎。該標準於 1995 年由 IEEE 正式化,標準編號為 1364-1995。大約在同一時間,一個名為 Analog Verilog International 的團體成立,旨在提出對 Verilog 的擴展,以支持類比和混合信號模擬。該團體的首個成果於 1996 年推出,當時發布了 Verilog-A 的語言定義。Verilog-A 並不打算直接與 Verilog-HDL 一起使用,而是一種具有相似語法和相關語義的語言,旨在建模類比系統並與 SPICE 類電路模擬引擎兼容。Verilog-A 的首個實作隨之而來:Cadence 提供了一個在其 Spectre 電路模擬器上運行的版本。隨著越來越多的 Verilog-A 實作問世,定義類比和混合信號擴展的團體繼續他們的工作,並於 2000 年發布了 Verilog-AMS 的定義。Verilog-AMS 結合了 Verilog-HDL 和 Verilog-A,並增加了額外的混合信號結構,提供了一種適用於類比、數位和混合信號系統的硬體描述語言。同樣,Cadence 首先發布了這種新語言的實作,名為 AMS Designer,該產品結合了他們的 Verilog 和 Spectre 模擬引擎。