State Machines in VHDL Dividers Vol. 3: State Machine Design for Arithmetic Processes (Volume 3)

Unlike multipliers, divider circuits are much more difficult. Four state machine designs for FPGA and ASIC devices are provided ranging from simple to high performance with suggestions for even higher performance. Unlike other books that provide high level explanation or an academic overview of techniques, this book provides everything to design dividers -- the first of its kind. Chapters are also used as a venue to introduce the reader to high performance strategies such higher performance adders, sign-digit representation and conversion, carry-save-form, and others. As with all books in this series, each design covered has a fully coded and fully functional design in VHDL as a state machine, with normalizing, rounding, overflow, and underflow included. Each design is also scalable in terms of operand size and the size of integer and fractional portions.