Sequential Logic and Verilog HDL Fundamentals

Joseph Cavanagh

Sequential Logic and Verilog HDL Fundamentals
  • 出版商: CRC
  • 出版日期: 2015-10-28
  • 售價: $7,840
  • 貴賓價: 9.5 折 $7,448
  • 語言: 英文
  • 頁數: 860
  • 裝訂: Hardcover
  • ISBN: 1498738222
  • ISBN-13: 9781498738224
  • 相關分類: Verilog

    • 海外代購書籍(需單獨結帳)

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商品描述

Sequential Logic and Verilog HDL Fundamentals discusses the analysis and synthesis of synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995.

The book concentrates on sequential logic design with a focus on the design of various Verilog HDL projects. Emphasis is placed on structured and rigorous design principles that can be applied to practical applications. Each step of the analysis and synthesis procedures is clearly delineated. Each method that is presented is expounded in sufficient detail with accompanying examples. Many analysis and synthesis examples use mixed-logic symbols incorporating both positive- and negative-input logic gates for NAND (not AND) and NOR (not OR) logic, while other examples utilize only positive-input logic gates. The use of mixed logic parallels the use of these symbols in the industry.

The book is intended to be a tutorial, and as such, is comprehensive and self-contained. All designs are carried through to completion―nothing is left unfinished or partially designed. Each chapter contains numerous problems of varying complexity to be designed by the reader using Verilog HDL design techniques. The Verilog HDL designs include the design module, the test bench module that tests the design for correct functionality, the outputs obtained from the test bench, and the waveforms obtained from the test bench.

Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL with numerous design examples to help the reader thoroughly understand this popular hardware description language. The book is designed for practicing electrical engineers, computer engineers, and computer scientists; for graduate students in electrical engineering, computer engineering, and computer science; and for senior-level undergraduate students.

商品描述(中文翻譯)

《Sequential Logic and Verilog HDL Fundamentals》討論了同步和非同步時序機器的分析和合成。這些機器是使用Verilog硬體描述語言（HDL）實現的，符合電氣和電子工程師學會（IEEE）的標準：1364-1995。

本書專注於以Verilog HDL設計各種項目的時序邏輯設計。強調結構化和嚴謹的設計原則，可應用於實際應用。清楚劃分了分析和合成過程的每一步。每個方法都有足夠的詳細說明和相應的示例。許多分析和合成示例使用混合邏輯符號，包括正輸入和負輸入的NAND（非AND）和NOR（非OR）邏輯閘，而其他示例僅使用正輸入邏輯閘。混合邏輯的使用與行業中使用這些符號的情況相對應。

本書旨在成為一本教程，因此內容全面且自成一體。所有設計都完整地進行到最後，沒有未完成或部分設計的情況。每章包含許多不同複雜度的問題，讓讀者使用Verilog HDL設計技術進行設計。Verilog HDL設計包括設計模塊、測試台模塊（用於測試設計的正確功能）、測試台獲得的輸出以及測試台獲得的波形。

《Sequential Logic and Verilog HDL Fundamentals》通過大量的設計示例，幫助讀者全面理解這種流行的硬體描述語言Verilog HDL。本書適用於實踐中的電氣工程師、計算機工程師和計算機科學家；電氣工程、計算機工程和計算機科學的研究生；以及高年級本科生。

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