Introduction to Logic Synthesis using Verilog HDL (原版:9781598291063)

Reese/Thornton

  • 出版商: Morgan and Claypool
  • 出版日期: 2006-10-25
  • 售價: $1,500
  • 貴賓價: 9.5$1,425
  • 語言: 英文
  • 頁數: 84
  • ISBN: 1598294040
  • ISBN-13: 9781598294040
  • 相關分類: Verilog

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Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.