Advanced ASIC Chip Synthesis: Using Synopsysa (R) Design Compilera (R) and Primetimea (R)

Bhatnagar, Himanshu

  • 出版商: Springer
  • 出版日期: 1999-05-31
  • 售價: $4,030
  • 貴賓價: 9.5$3,829
  • 語言: 英文
  • 頁數: 316
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 0792385373
  • ISBN-13: 9780792385370
  • 相關分類: VLSI
  • 海外代購書籍(需單獨結帳)

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Foreword. Preface. Acknowledgements. About the Author. 1. ASIC Design Methodology. 2. Tutorial. 3. Basic Concepts. 4. Synopsys Technology Library. 5. Partitioning and Coding Styles. 6. Constraining Designs. 7. Optimizing Designs. 8. Design for Test. 9. Links to Layout & Post-Layout Optimization. 10. SDF Generation. 11. PrimeTime Basics. 12. Static Timing Analysis. Appendix. Index.