Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them(快遞進口)
暫譯: Verilog 與 SystemVerilog 常見陷阱：101 個常見程式錯誤及其避免方法

This book will help engineers write better Verilog/SystemVerilog design and verification code as well as deliver digital designs to market more quickly. It shows over 100 common coding mistakes that can be made with the Verilog and SystemVerilog languages. Each example explains in detail the symptoms of the error, the languages rules that cover the error, and the correct coding style to avoid the error. The book helps digital design and verification engineers to recognize, and avoid, these common coding mistakes. Many of these errors are very subtle, and can potentially cost hours or days of lost engineering time trying to find and debug them.