RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design (Paperback)

Stuart Sutherland

  • 出版商: W. W. Norton
  • 出版日期: 2017-06-10
  • 售價: $4,230
  • 貴賓價: 9.5$4,019
  • 語言: 英文
  • 頁數: 488
  • 裝訂: Paperback
  • ISBN: 1546776346
  • ISBN-13: 9781546776345
  • 相關分類: FPGAVerilog
  • 立即出貨 (庫存=1)

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商品描述

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. The creator of the original Verilog Language, Phil Moorby says about this book (an excerpt from the book's Foreword): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe not even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.”

商品描述(中文翻譯)

這本書既是一本教程,也是一本參考書,針對使用SystemVerilog硬體描述語言(HDL)設計ASIC和FPGA的工程師。本書展示了如何在註冊傳輸層(RTL)上編寫SystemVerilog模型,以正確模擬和綜合,並著重於適當的編碼風格和最佳實踐。SystemVerilog是原始Verilog語言的最新一代,並添加了許多重要功能,以有效且更準確地模擬越來越複雜的設計。本書反映了SystemVerilog-2012/2017標準。本書適用於已經了解或正在學習數字設計工程的工程師。本書不介紹數字設計理論;它展示了如何應用該理論來編寫正確模擬和綜合的RTL模型。原始Verilog語言的創造者Phil Moorby在本書的前言中說道:“許多關於SystemVerilog設計方面的已出版教科書假設讀者熟悉Verilog,並僅解釋新的擴展。是時候放棄這些踏腳石,教授一種一致且簡潔的語言,並且可能根本不提及舊的方法!如果您是數字系統的設計師,或者是在這些設計中尋找錯誤的驗證工程師,那麼SystemVerilog將為您提供顯著的好處,而本書是學習SystemVerilog設計方面的絕佳資源。”