System Verilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications, 3/e (Hardcover)

Mehta, Ashok B.



This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. 


This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.

·         Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;

·         Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies;

·         Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;

·         Explains each concept in a step-by-step fashion and applies it to a practical real life example;


·         Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.


本書提供了一個實踐導向的指南,介紹了SystemVerilog Assertions和Functional Coverage的語言和方法論。讀者將從逐步學習SystemVerilog Assertions和Functional Coverage的語言和方法論細微之處中受益,這將使他們能夠發現隱藏和難以找到的錯誤,直接指向錯誤的源頭,提供一種清晰簡單的方式來建模複雜的時序檢查並客觀回答“我們是否在功能上驗證了所有內容”的問題。本書由ASIC/SoC/CPU和FPGA設計和驗證的專業最終用戶撰寫,通過易於理解的示例、模擬日誌和來自實際項目的應用來解釋每個概念。讀者將能夠處理功能驗證的複雜檢查器建模和功能覆蓋的全面覆蓋模型,從而大大減少設計、調試和覆蓋的時間。


· 完整涵蓋了最新的IEEE-1800 2012 LRM語法和語義;
· 同時涵蓋了SystemVerilog Assertions和SystemVerilog Functional Coverage語言和方法論;
· 提供了基於斷言的驗證和功能覆蓋方法論的實際應用;
· 以逐步方式解釋每個概念並將其應用於實際的生活示例;
· 包括6個實際實驗室,讓讀者能夠實踐本書中解釋的概念。



Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that establish Reuse of Verification Environment from ESL to RTL. Lately, he has been researching 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification.

Ashok earned an MSEE from University of Missouri. He holds 18 U.S. Patents in the field of SoC and 3DIC design verification.






Ashok Mehta在ASIC/SoC設計和驗證領域工作超過20年。他的職業生涯始於Digital Equipment Corporation (DEC),擔任CPU設計工程師。之後他在Data General、Intel(第一個Pentium設計團隊)工作,並在幾家初創公司後加入了Applied Micro和TSMC。他是Verilog的早期採用者,並參與了Verilog、VHDL、iHDL(Intel HDL)和SDF(標準延遲格式)技術小組。他也一直支持ESL(電子系統級)設計,在TSMC發布了兩個行業標準的參考流程,從ESL到RTL建立了驗證環境的重用。最近,他在TSMC研究了3DIC設計驗證的挑戰,其中SystemVerilog Assertions在堆疊式芯片SoC設計驗證中起到了重要作用。