ASIC Design and Synthesis: RTL Design Using Verilog

Taraate, Vaibbhav

ASIC Design and Synthesis: RTL Design Using Verilog
  • 出版商: Springer
  • 出版日期: 2022-01-08
  • 售價: $6,250
  • 貴賓價: 9.5 折 $5,938
  • 語言: 英文
  • 頁數: 354
  • 裝訂: Quality Paper - also called trade paper
  • ISBN: 9813346442
  • ISBN-13: 9789813346444
  • 相關分類: 電子電路電機類、嵌入式系統

    • 海外代購書籍(需單獨結帳)

相關主題

商品描述

Chapter 1. Introduction.

Chapter 2. Design using CMOS.

Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL).

Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).

Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL).

Chapter 6. ASIC design guidelines.

Chapter 7. ASIC RTL Verification.

Chapter 8. FSM using VHDL and synthesis.

Chapter 9. ASIC design improvement techniques.

Chapter 10. ASIC Synthesis using Synopsys DC.

Chapter 11. Design for Testability.

Chapter 12. Static timing analysis.

Chapter 13. Multiple Clock domain designs.

Chapter 14. Low power ASIC design.

Chapter 15. ASIC Physical design.

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