VHDL Design Representation and Synthesis, 2/e
James R. Armstrong , F. Gail Gray
- 出版商: Prentice Hall
- 出版日期: 2000-01-31
- 售價: $1,150
- 貴賓價: 9.8 折 $1,127
- 語言: 英文
- 頁數: 651
- ISBN: 9867594266
- ISBN-13: 9789867594266
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商品描述
For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.
Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.
Table of Contents
Preface.
1. Structured Design Concepts.
2. Design Tools.
3. Basic Features of VHDL.
3. Lexical Description. Character Set.
4. Basic VHDL Modeling Techniques.
5. Algorithmic Level Design.
6. Register Level Design.
7. Gate Level and ASIC Library Modeling.
8. HDL-Based Design Techniques.
9. ASICs and the ASIC Design Process.
10. Modeling for Synthesis.
11. Integration of VHDL into a Top-Down Design Methodology.
12. Synthesis Algorithms for Design Automation.
Index.
References.
About the Authors.
About the CD.
Index.