For senior/graduate-level courses in Advanced Digital Design and Advanced
Digital Logic in departments of electrical engineering, computer engineering,
and computer science.
Intended to teach a synthesis-based approach to design using a hardware
description language (i.e., VHDL), this text focuses on the synthesis process in
how to translate VHDL descriptions into gate level logic. It teaches the VHDL
language in detail, describes modeling at three different levels of abstraction
(algorithmic, data flow, and gate level), and explains the ASIC Design Process.
Illustrations of synthesis with standard cell libraries and FPGAs are given
using Synopsys and Xilinx tools.
Table of Contents
1. Structured Design Concepts.
The Abstraction Hierarchy. Textual vs Pictorial
Representations. Types of Behavioral Descriptions. Design Process. Structural
Design Decomposition. The Digital Design Space.
2. Design Tools.
CAD Tool Taxonomy. Schematic Editors.
Simulators. The Simulation System. Simulation Aids. Applications of Simulation.
3. Basic Features of VHDL.
Major Language Constructs.
3. Lexical Description. Character Set.
VHDL Source File. Data Types. Data Objects.
Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL
4. Basic VHDL Modeling Techniques.
Modeling Delay in VHDL. The VHDL Scheduling
Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives.
5. Algorithmic Level Design.
General Algorithmic Model Development in the
Behavioral Domain. Representation of System Interconnections. Algorithmic
Modeling of Systems.
6. Register Level Design.
Transition from Algorithmic to Data Flow
Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine.
7. Gate Level and ASIC Library Modeling.
Accurate Gate Level Modeling. Error Checking.
Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate
Level Models. Modeling Races and Hazards. Approaches to Delay Control.
8. HDL-Based Design Techniques.
Design of Combinational Logic Circuits. Design
of Sequential Logic Circuits. Design of Microprogrammed Control Units.
9. ASICs and the ASIC Design Process.
What is an ASIC? ASIC Circuit Technology. Types
of ASICs. The ASIC Design Process. FPGA Synthesis.
10. Modeling for Synthesis.
Behavioral Model Development. The Semantics of
Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational
Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits.
Shared Resources. Flattening and Structuring. Effect of Modeling Style On
11. Integration of VHDL into a Top-Down Design Methodology.
Top-Down Design Methodology. Sobel Edge
Detection Algorithm. System Requirements Level. System Definition Level.
Architecture Design. Detailed Design at the RTL Level. Detailed Design at the
12. Synthesis Algorithms for Design Automation.
Benefits of Algorithmic Synthesis. Algorithmic
Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art
in High-Level Synthesis. Automated Synthesis of VHDL Constructs.
About the Authors.
About the CD.