VHDL Design Representation and Synthesis, 2/e

James R. Armstrong , F. Gail Gray

VHDL Design Representation and Synthesis, 2/e
  • 出版商: Prentice Hall
  • 出版日期: 2000-01-31
  • 售價: $1,150
  • 貴賓價: 9.8 折 $1,127
  • 語言: 英文
  • 頁數: 651
  • ISBN: 9867594266
  • ISBN-13: 9789867594266

    • 下單後立即進貨 (約5~7天)

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商品描述

For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.

Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.

Table of Contents

Preface.
1. Structured Design Concepts.

The Abstraction Hierarchy. Textual vs Pictorial Representations. Types of Behavioral Descriptions. Design Process. Structural Design Decomposition. The Digital Design Space.


2. Design Tools.

CAD Tool Taxonomy. Schematic Editors. Simulators. The Simulation System. Simulation Aids. Applications of Simulation. Synthesis Tools.


3. Basic Features of VHDL.

Major Language Constructs.


3. Lexical Description. Character Set.

VHDL Source File. Data Types. Data Objects. Language Statements. Advanced Features of VHDL. The Formal Nature of VHDL. VHDL 93. Summary.


4. Basic VHDL Modeling Techniques.

Modeling Delay in VHDL. The VHDL Scheduling Algorithm. Modeling Combinational and Sequential Logic. Logic Primitives.


5. Algorithmic Level Design.

General Algorithmic Model Development in the Behavioral Domain. Representation of System Interconnections. Algorithmic Modeling of Systems.


6. Register Level Design.

Transition from Algorithmic to Data Flow Descriptions. Timing Analysis. Control Unit Design. Ultimate RISC Machine.


7. Gate Level and ASIC Library Modeling.

Accurate Gate Level Modeling. Error Checking. Multivalued Logic for Gate Level Modeling. Configuration Declarations for Gate Level Models. Modeling Races and Hazards. Approaches to Delay Control.


8. HDL-Based Design Techniques.

Design of Combinational Logic Circuits. Design of Sequential Logic Circuits. Design of Microprogrammed Control Units.


9. ASICs and the ASIC Design Process.

What is an ASIC? ASIC Circuit Technology. Types of ASICs. The ASIC Design Process. FPGA Synthesis.


10. Modeling for Synthesis.

Behavioral Model Development. The Semantics of Simulation and Synthesis. Modeling Sequential Behavior. Modeling Combinational Circuits for Synthesis. Inferred Latches and Don't Cares. Tristate Circuits. Shared Resources. Flattening and Structuring. Effect of Modeling Style On Circuit Complexity.


11. Integration of VHDL into a Top-Down Design Methodology.

Top-Down Design Methodology. Sobel Edge Detection Algorithm. System Requirements Level. System Definition Level. Architecture Design. Detailed Design at the RTL Level. Detailed Design at the Gate Level.


12. Synthesis Algorithms for Design Automation.

Benefits of Algorithmic Synthesis. Algorithmic Synthesis Tasks. Scheduling Techniques. Allocation Techniques. State of the Art in High-Level Synthesis. Automated Synthesis of VHDL Constructs.


Index.
References.
About the Authors.
About the CD.
Index.

商品描述(中文翻譯)

這本書適用於電機工程、電腦工程和計算機科學等專業的高級/研究生級別的高級數字設計和高級數字邏輯課程。該教材旨在教授一種基於綜合的設計方法，使用硬件描述語言（即VHDL），重點在於如何將VHDL描述轉換為閘級邏輯。它詳細介紹了VHDL語言，描述了三個不同抽象層次（算法、數據流和閘級）的建模，並解釋了ASIC設計過程。使用Synopsys和Xilinx工具提供了使用標準單元庫和FPGA的綜合示例。


目錄


前言。
1. 結構化設計概念。


抽象層次結構。文字與圖像表示。行為描述類型。設計過程。結構化設計分解。數字設計空間。



2. 設計工具。


CAD工具分類。原理圖編輯器。模擬器。模擬系統。模擬輔助工具。模擬應用。綜合工具。



3. VHDL的基本特性。


主要語言結構。



3. 語法描述。字符集。


VHDL源文件。數據類型。數據對象。語言語句。VHDL的高級特性。VHDL的形式性質。VHDL 93。總結。



4. 基本的VHDL建模技術。


VHDL中的延遲建模。VHDL調度算法。組合邏輯和時序邏輯建模。邏輯原語。



5. 算法級設計。


行為域中的通用算法模型開發。系統互連的表示。系統的算法建模。



6. 寄存器級設計。


從算法到數據流描述的轉換。時序分析。控制單元設計。最終的RISC機器。



7. 閘級和ASIC庫建模。


準確的閘級建模。錯誤檢查。閘級建模的多值邏輯。閘級模型的配置聲明。競態和危害建模。延遲控制方法。



8. 基於HDL的設計技術。


組合邏輯電路設計。時序邏輯電路設計。微程控制單元設計。



9. ASIC和ASIC設計過程。


什麼是ASIC？ASIC電路技術。ASIC的類型。ASIC設計過程。FPGA綜合。



10. 綜合建模。


行為模型開發。模擬和綜合的語義。時序行為建模。用於綜合的組合電路建模。推斷的觸發器和不關心值。三態電路。共享資源。展平和結構化。建模風格對電路複雜性的影響。



11. VHDL在自頂向下設計方法中的整合。


自頂向下設計方法。Sobel邊緣檢測算法。系統需求層次。系統定義層次。架構設計。在RTL層次進行詳細設計。在閘級進行詳細設計。



12. 設計自動化的綜合算法。


算法綜合的好處。算法綜合任務。調度技術。分配技術。高級綜合的現狀。VHDL構造的自動綜合。

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