100 Power Tips For FPGA Designers (Paperback)
暫譯: FPGA 設計師的 100 個實用技巧 (平裝本)
Evgeni Stavinov
- 出版商: CreateSpace Independ
- 出版日期: 2011-06-17
- 售價: $1,820
- 貴賓價: 9.5 折 $1,729
- 語言: 英文
- 頁數: 474
- 裝訂: Paperback
- ISBN: 1461186293
- ISBN-13: 9781461186298
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相關分類:
FPGA
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相關主題
商品描述
This book is a collection of short articles on various aspects of FPGA design: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, design methodologies, performance, area and power optimizations, RTL coding, IP core selection, and many others. The book is intended for system architects, design engineers, and students who want to improve their FPGA design skills. Both novice and seasoned logic and hardware engineers can find bits of useful information. This book is written by a practicing FPGA logic designer, and contains a lot of illustrations, code examples, and scripts. Rather than providing information applicable to all FPGA vendors, this book edition focuses on Xilinx Virtex-6 and Spartan-6 FPGA families. Code examples are written in Verilog HDL. All code examples, scripts, and projects provided in the book are available on accompanying website: http://outputlogic.com/100_fpga_power_tips
商品描述(中文翻譯)
本書是關於FPGA設計各個方面的短文集，包括合成、模擬、移植ASIC設計、樓層規劃和時序收斂、設計方法論、性能、面積和功耗優化、RTL編碼、IP核心選擇等多個主題。
本書的目標讀者為系統架構師、設計工程師以及希望提升FPGA設計技能的學生。無論是新手還是資深的邏輯和硬體工程師，都能找到有用的信息。
本書由一位實踐中的FPGA邏輯設計師撰寫，包含大量插圖、程式碼範例和腳本。本書版本專注於Xilinx Virtex-6和Spartan-6 FPGA系列，而非提供適用於所有FPGA供應商的信息。程式碼範例使用Verilog HDL編寫。本書中提供的所有程式碼範例、腳本和專案均可在附帶網站上獲得：http://outputlogic.com/100_fpga_power_tips
